Roy Karl Potter

Array ( [id] => 3944598 [patent_doc_number] => 05973390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Chip electronic part' [patent_app_type] => 1 [patent_app_number] => 8/921508 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1977 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973390.pdf [firstpage_image] =>[orig_patent_app_number] => 921508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4244666 [patent_doc_number] => 06091156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Semiconductor pellet having plural chips' [patent_app_type] => 1 [patent_app_number] => 8/920905 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3328 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091156.pdf [firstpage_image] =>[orig_patent_app_number] => 920905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159179 [patent_doc_number] => 06124633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Vertical interconnect process for silicon segments with thermally conductive epoxy preform' [patent_app_type] => 1 [patent_app_number] => 8/918501 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 8144 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124633.pdf [firstpage_image] =>[orig_patent_app_number] => 918501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366597 [patent_doc_number] => 06255726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Vertical interconnect process for silicon segments with dielectric isolation' [patent_app_type] => 1 [patent_app_number] => 8/915620 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 7994 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255726.pdf [firstpage_image] =>[orig_patent_app_number] => 915620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4102220 [patent_doc_number] => 06097100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Resin sealed semiconductor devices and a process for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/915334 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 8825 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097100.pdf [firstpage_image] =>[orig_patent_app_number] => 915334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3766941 [patent_doc_number] => 05844308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Integrated circuit anti-bridging leads design' [patent_app_type] => 1 [patent_app_number] => 8/915268 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2511 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844308.pdf [firstpage_image] =>[orig_patent_app_number] => 915268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4242972 [patent_doc_number] => 06144095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Metallization layer' [patent_app_type] => 1 [patent_app_number] => 8/912051 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1839 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144095.pdf [firstpage_image] =>[orig_patent_app_number] => 912051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4070405 [patent_doc_number] => 06069026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Semiconductor device and method of fabrication' [patent_app_type] => 1 [patent_app_number] => 8/912266 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 25 [patent_no_of_words] => 3978 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069026.pdf [firstpage_image] =>[orig_patent_app_number] => 912266 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4076183 [patent_doc_number] => 06069405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'High capacitance mirror driver cell' [patent_app_type] => 1 [patent_app_number] => 8/910087 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3195 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069405.pdf [firstpage_image] =>[orig_patent_app_number] => 910087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950443 [patent_doc_number] => 05990543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Reframed chip-on-tape die' [patent_app_type] => 1 [patent_app_number] => 8/908404 [patent_app_country] => US [patent_app_date] => 1997-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2691 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990543.pdf [firstpage_image] =>[orig_patent_app_number] => 908404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405756 [patent_doc_number] => 06232213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method of making a semiconductor chip package' [patent_app_type] => 1 [patent_app_number] => 8/910500 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2485 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232213.pdf [firstpage_image] =>[orig_patent_app_number] => 910500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4038382 [patent_doc_number] => 05994771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Semiconductor package with multilayer circuit, and semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/875484 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3192 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994771.pdf [firstpage_image] =>[orig_patent_app_number] => 875484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161615 [patent_doc_number] => 06107689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/902093 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 5632 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107689.pdf [firstpage_image] =>[orig_patent_app_number] => 902093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4090595 [patent_doc_number] => 06025617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Microelectronic devices having increased impurity concentration between a metal silicide contact surface' [patent_app_type] => 1 [patent_app_number] => 8/899554 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2578 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025617.pdf [firstpage_image] =>[orig_patent_app_number] => 899554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3909281 [patent_doc_number] => 05898216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Micromodule with protection barriers and a method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/897352 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2887 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898216.pdf [firstpage_image] =>[orig_patent_app_number] => 897352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4148273 [patent_doc_number] => 06031292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Semiconductor device, interposer for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/896836 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3803 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031292.pdf [firstpage_image] =>[orig_patent_app_number] => 896836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950635 [patent_doc_number] => 05990556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Stacked thin film assembly' [patent_app_type] => 1 [patent_app_number] => 8/892736 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 7882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990556.pdf [firstpage_image] =>[orig_patent_app_number] => 892736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187526 [patent_doc_number] => 06020645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Semiconductor device with semiconductor chip bonded face down on circuit-carrying substrate' [patent_app_type] => 1 [patent_app_number] => 8/893420 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3181 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020645.pdf [firstpage_image] =>[orig_patent_app_number] => 893420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932142 [patent_doc_number] => 05952719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Metal ball grid electronic package having improved solder joint' [patent_app_type] => 1 [patent_app_number] => 8/891446 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952719.pdf [firstpage_image] =>[orig_patent_app_number] => 891446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3939187 [patent_doc_number] => 05939778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Integrated circuit chip package' [patent_app_type] => 1 [patent_app_number] => 8/889378 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4090 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939778.pdf [firstpage_image] =>[orig_patent_app_number] => 889378 [rel_patent_id] =>[rel_patent_doc_number] =>)