Search

Rupal Dharia

Supervisory Patent Examiner (ID: 2589, Phone: (571)272-3880 , Office: P/2400 )

Most Active Art Unit
2181
Art Unit(s)
2181, 2781, 2492, 2305, 2400, 2100, 2456, 2141, 2189, 2443, 2441
Total Applications
412
Issued Applications
349
Pending Applications
25
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1567351 [patent_doc_number] => 06363445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method of bus arbitration using requesting device bandwidth and priority ranking' [patent_app_type] => B1 [patent_app_number] => 09/173573 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4024 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363445.pdf [firstpage_image] =>[orig_patent_app_number] => 09173573 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/173573
Method of bus arbitration using requesting device bandwidth and priority ranking Oct 14, 1998 Issued
Array ( [id] => 4292019 [patent_doc_number] => 06247084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Integrated circuit with unified memory system and dual bus architecture' [patent_app_type] => 1 [patent_app_number] => 9/166262 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 63 [patent_no_of_words] => 21619 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247084.pdf [firstpage_image] =>[orig_patent_app_number] => 166262 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166262
Integrated circuit with unified memory system and dual bus architecture Oct 4, 1998 Issued
Array ( [id] => 4374491 [patent_doc_number] => 06170029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Voltage overshoot control in hot plug system' [patent_app_type] => 1 [patent_app_number] => 9/163922 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3042 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170029.pdf [firstpage_image] =>[orig_patent_app_number] => 163922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163922
Voltage overshoot control in hot plug system Sep 29, 1998 Issued
09/162975 METHOD AND APPARATUS FOR MULTIPLE TIER INTELLIGENT BUS ARBITRATION ON A PCI TO PCI BRIDGE Sep 28, 1998 Abandoned
Array ( [id] => 1572222 [patent_doc_number] => 06378013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'System for assessing performance of computer systems' [patent_app_type] => B1 [patent_app_number] => 09/156370 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3062 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378013.pdf [firstpage_image] =>[orig_patent_app_number] => 09156370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156370
System for assessing performance of computer systems Sep 16, 1998 Issued
Array ( [id] => 4422154 [patent_doc_number] => 06272572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Apparatus and method for transmitting and receiving passenger service system and telephone signals over a network' [patent_app_type] => 1 [patent_app_number] => 9/154256 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4330 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272572.pdf [firstpage_image] =>[orig_patent_app_number] => 154256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154256
Apparatus and method for transmitting and receiving passenger service system and telephone signals over a network Sep 15, 1998 Issued
Array ( [id] => 1553086 [patent_doc_number] => 06446212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Processor having an extended operating voltage range' [patent_app_type] => B1 [patent_app_number] => 09/141899 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1679 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446212.pdf [firstpage_image] =>[orig_patent_app_number] => 09141899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141899
Processor having an extended operating voltage range Aug 27, 1998 Issued
Array ( [id] => 4268754 [patent_doc_number] => 06138187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method and system for increasing spatial reuse in a serial storage architecture subsystem' [patent_app_type] => 1 [patent_app_number] => 9/137884 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3920 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138187.pdf [firstpage_image] =>[orig_patent_app_number] => 137884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137884
Method and system for increasing spatial reuse in a serial storage architecture subsystem Aug 20, 1998 Issued
Array ( [id] => 4109824 [patent_doc_number] => 06134623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method and system for taking advantage of a pre-stage of data between a host processor and a memory system' [patent_app_type] => 1 [patent_app_number] => 9/137670 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2512 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134623.pdf [firstpage_image] =>[orig_patent_app_number] => 137670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137670
Method and system for taking advantage of a pre-stage of data between a host processor and a memory system Aug 20, 1998 Issued
Array ( [id] => 6908549 [patent_doc_number] => 20010011316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'DISK STORAGE APPARATUS AND SYSTEM UTILIZING RECORDING MEDIUMS OF DIFFERENT TYPES' [patent_app_type] => new [patent_app_number] => 09/135465 [patent_app_country] => US [patent_app_date] => 1998-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4377 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011316.pdf [firstpage_image] =>[orig_patent_app_number] => 09135465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135465
DISK STORAGE APPARATUS AND SYSTEM UTILIZING RECORDING MEDIUMS OF DIFFERENT TYPES Aug 16, 1998 Abandoned
Array ( [id] => 4374429 [patent_doc_number] => 06170025 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Distributed computer system supporting remote interrupts and lock mechanism' [patent_app_type] => 1 [patent_app_number] => 9/132324 [patent_app_country] => US [patent_app_date] => 1998-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12969 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170025.pdf [firstpage_image] =>[orig_patent_app_number] => 132324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/132324
Distributed computer system supporting remote interrupts and lock mechanism Aug 10, 1998 Issued
Array ( [id] => 4366050 [patent_doc_number] => 06286072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'System and method for synchronizing data communication between asynchronous buses' [patent_app_type] => 1 [patent_app_number] => 9/131948 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3992 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286072.pdf [firstpage_image] =>[orig_patent_app_number] => 131948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/131948
System and method for synchronizing data communication between asynchronous buses Aug 9, 1998 Issued
Array ( [id] => 4316790 [patent_doc_number] => 06182121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method and apparatus for a physical storage architecture having an improved information storage and retrieval system for a shared file environment' [patent_app_type] => 1 [patent_app_number] => 9/128922 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 43 [patent_no_of_words] => 18966 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182121.pdf [firstpage_image] =>[orig_patent_app_number] => 128922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/128922
Method and apparatus for a physical storage architecture having an improved information storage and retrieval system for a shared file environment Aug 3, 1998 Issued
Array ( [id] => 4373887 [patent_doc_number] => 06292862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Bridge module' [patent_app_type] => 1 [patent_app_number] => 9/123825 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3293 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292862.pdf [firstpage_image] =>[orig_patent_app_number] => 123825 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123825
Bridge module Jul 27, 1998 Issued
Array ( [id] => 4366615 [patent_doc_number] => 06286109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method and apparatus for reducing heat generation in a portable computer' [patent_app_type] => 1 [patent_app_number] => 9/107648 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2443 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286109.pdf [firstpage_image] =>[orig_patent_app_number] => 107648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107648
Method and apparatus for reducing heat generation in a portable computer Jun 29, 1998 Issued
Array ( [id] => 4202658 [patent_doc_number] => 06094725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Magnetic disk apparatus' [patent_app_type] => 1 [patent_app_number] => 9/105396 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 56 [patent_no_of_words] => 27976 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094725.pdf [firstpage_image] =>[orig_patent_app_number] => 105396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105396
Magnetic disk apparatus Jun 25, 1998 Issued
Array ( [id] => 4290818 [patent_doc_number] => 06308279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method and apparatus for power mode transition in a multi-thread processor' [patent_app_type] => 1 [patent_app_number] => 9/083281 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2437 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308279.pdf [firstpage_image] =>[orig_patent_app_number] => 083281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083281
Method and apparatus for power mode transition in a multi-thread processor May 21, 1998 Issued
Array ( [id] => 4260611 [patent_doc_number] => 06092205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Device for automatically locking a power button in a computer' [patent_app_type] => 1 [patent_app_number] => 9/079444 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2852 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092205.pdf [firstpage_image] =>[orig_patent_app_number] => 079444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/079444
Device for automatically locking a power button in a computer May 14, 1998 Issued
Array ( [id] => 4298281 [patent_doc_number] => 06282593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Extension of electronic buses and their bus protocols using signal-propagation timing compensation' [patent_app_type] => 1 [patent_app_number] => 9/075450 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5600 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282593.pdf [firstpage_image] =>[orig_patent_app_number] => 075450 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075450
Extension of electronic buses and their bus protocols using signal-propagation timing compensation May 7, 1998 Issued
Array ( [id] => 4392391 [patent_doc_number] => 06289467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Installation of processor and power supply modules in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 9/075026 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3296 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289467.pdf [firstpage_image] =>[orig_patent_app_number] => 075026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075026
Installation of processor and power supply modules in a multiprocessor system May 7, 1998 Issued
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