
Rupal Dharia
Supervisory Patent Examiner (ID: 14113, Phone: (571)272-3880 , Office: P/2400 )
| Most Active Art Unit | 2181 |
| Art Unit(s) | 2400, 2492, 2189, 2443, 2781, 2181, 2305, 2456, 2100, 2441, 2141 |
| Total Applications | 417 |
| Issued Applications | 349 |
| Pending Applications | 30 |
| Abandoned Applications | 39 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4149105
[patent_doc_number] => 06016558
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Communication event/message tracing method for RPC-based distribution processing program'
[patent_app_type] => 1
[patent_app_number] => 9/006905
[patent_app_country] => US
[patent_app_date] => 1998-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3001
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 406
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/016/06016558.pdf
[firstpage_image] =>[orig_patent_app_number] => 006905
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/006905 | Communication event/message tracing method for RPC-based distribution processing program | Jan 13, 1998 | Issued |
Array
(
[id] => 3933149
[patent_doc_number] => 06003138
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Computer peripheral power distribution device'
[patent_app_type] => 1
[patent_app_number] => 9/006153
[patent_app_country] => US
[patent_app_date] => 1998-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 890
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/003/06003138.pdf
[firstpage_image] =>[orig_patent_app_number] => 006153
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/006153 | Computer peripheral power distribution device | Jan 12, 1998 | Issued |
Array
(
[id] => 4299453
[patent_doc_number] => 06282669
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Ethernet communication redundancy method'
[patent_app_type] => 1
[patent_app_number] => 9/004945
[patent_app_country] => US
[patent_app_date] => 1998-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3755
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/282/06282669.pdf
[firstpage_image] =>[orig_patent_app_number] => 004945
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/004945 | Ethernet communication redundancy method | Jan 8, 1998 | Issued |
Array
(
[id] => 7638642
[patent_doc_number] => 06397279
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Smart retry system that reduces wasted bus transactions associated with master retries'
[patent_app_type] => B1
[patent_app_number] => 09/003864
[patent_app_country] => US
[patent_app_date] => 1998-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5382
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 6
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/397/06397279.pdf
[firstpage_image] =>[orig_patent_app_number] => 09003864
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/003864 | Smart retry system that reduces wasted bus transactions associated with master retries | Jan 6, 1998 | Issued |
Array
(
[id] => 4424906
[patent_doc_number] => 06230270
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Integrated circuit identification system'
[patent_app_type] => 1
[patent_app_number] => 9/002464
[patent_app_country] => US
[patent_app_date] => 1998-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3976
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/230/06230270.pdf
[firstpage_image] =>[orig_patent_app_number] => 002464
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/002464 | Integrated circuit identification system | Jan 1, 1998 | Issued |
Array
(
[id] => 4238766
[patent_doc_number] => 06088754
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Generic serial interface with automatic reconfigurability'
[patent_app_type] => 1
[patent_app_number] => 9/001352
[patent_app_country] => US
[patent_app_date] => 1997-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 25
[patent_no_of_words] => 4407
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/088/06088754.pdf
[firstpage_image] =>[orig_patent_app_number] => 001352
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/001352 | Generic serial interface with automatic reconfigurability | Dec 30, 1997 | Issued |
Array
(
[id] => 4152199
[patent_doc_number] => 06148352
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Scalable modular data storage system'
[patent_app_type] => 1
[patent_app_number] => 8/997962
[patent_app_country] => US
[patent_app_date] => 1997-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 4721
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/148/06148352.pdf
[firstpage_image] =>[orig_patent_app_number] => 997962
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997962 | Scalable modular data storage system | Dec 23, 1997 | Issued |
Array
(
[id] => 4101010
[patent_doc_number] => 06163827
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Method and apparatus for round-robin flash channel arbitration'
[patent_app_type] => 1
[patent_app_number] => 8/991254
[patent_app_country] => US
[patent_app_date] => 1997-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 1851
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/163/06163827.pdf
[firstpage_image] =>[orig_patent_app_number] => 991254
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991254 | Method and apparatus for round-robin flash channel arbitration | Dec 15, 1997 | Issued |
Array
(
[id] => 1431399
[patent_doc_number] => 06523129
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-18
[patent_title] => 'Method of preventing computer malfunction during a change of power consumption states via dynamic adjustment of core voltage'
[patent_app_type] => B1
[patent_app_number] => 08/991107
[patent_app_country] => US
[patent_app_date] => 1997-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3711
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/523/06523129.pdf
[firstpage_image] =>[orig_patent_app_number] => 08991107
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991107 | Method of preventing computer malfunction during a change of power consumption states via dynamic adjustment of core voltage | Dec 15, 1997 | Issued |
Array
(
[id] => 4373858
[patent_doc_number] => 06292860
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Method for preventing deadlock by suspending operation of processors, bridges, and devices'
[patent_app_type] => 1
[patent_app_number] => 8/991697
[patent_app_country] => US
[patent_app_date] => 1997-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2641
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/292/06292860.pdf
[firstpage_image] =>[orig_patent_app_number] => 991697
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/991697 | Method for preventing deadlock by suspending operation of processors, bridges, and devices | Dec 15, 1997 | Issued |
Array
(
[id] => 4374538
[patent_doc_number] => 06170032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Priority encoder circuit'
[patent_app_type] => 1
[patent_app_number] => 8/990478
[patent_app_country] => US
[patent_app_date] => 1997-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 4615
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/170/06170032.pdf
[firstpage_image] =>[orig_patent_app_number] => 990478
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990478 | Priority encoder circuit | Dec 14, 1997 | Issued |
Array
(
[id] => 4376251
[patent_doc_number] => 06219741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Transactions supporting interrupt destination redirection and level triggered interrupt semantics'
[patent_app_type] => 1
[patent_app_number] => 8/988232
[patent_app_country] => US
[patent_app_date] => 1997-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 6914
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/219/06219741.pdf
[firstpage_image] =>[orig_patent_app_number] => 988232
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988232 | Transactions supporting interrupt destination redirection and level triggered interrupt semantics | Dec 9, 1997 | Issued |
Array
(
[id] => 4334967
[patent_doc_number] => 06243780
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Interface of a monitor communicating with personal computer'
[patent_app_type] => 1
[patent_app_number] => 8/979118
[patent_app_country] => US
[patent_app_date] => 1997-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2781
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/243/06243780.pdf
[firstpage_image] =>[orig_patent_app_number] => 979118
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/979118 | Interface of a monitor communicating with personal computer | Nov 25, 1997 | Issued |
Array
(
[id] => 4198642
[patent_doc_number] => 06038613
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Prefetching and storing device work information from multiple data storage devices'
[patent_app_type] => 1
[patent_app_number] => 8/971085
[patent_app_country] => US
[patent_app_date] => 1997-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5222
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/038/06038613.pdf
[firstpage_image] =>[orig_patent_app_number] => 971085
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/971085 | Prefetching and storing device work information from multiple data storage devices | Nov 13, 1997 | Issued |
| 08/962624 | AUTOMATIC BACKUP BASED ON DISK DRIVE CONDITION | Nov 2, 1997 | Abandoned |
Array
(
[id] => 3802384
[patent_doc_number] => 05822545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Method and apparatus for eliminating electromagnetic interference and noise caused by all unnecessary switching/toggling of bus signals'
[patent_app_type] => 1
[patent_app_number] => 8/960585
[patent_app_country] => US
[patent_app_date] => 1997-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 3329
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/822/05822545.pdf
[firstpage_image] =>[orig_patent_app_number] => 960585
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/960585 | Method and apparatus for eliminating electromagnetic interference and noise caused by all unnecessary switching/toggling of bus signals | Oct 28, 1997 | Issued |
Array
(
[id] => 4109546
[patent_doc_number] => 06134604
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Communication apparatus for communicating with a plurality of communication control units cascade-connected'
[patent_app_type] => 1
[patent_app_number] => 8/958561
[patent_app_country] => US
[patent_app_date] => 1997-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 4972
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/134/06134604.pdf
[firstpage_image] =>[orig_patent_app_number] => 958561
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/958561 | Communication apparatus for communicating with a plurality of communication control units cascade-connected | Oct 26, 1997 | Issued |
Array
(
[id] => 4239789
[patent_doc_number] => 06012104
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Method and apparatus for dynamic extension of channel programs'
[patent_app_type] => 1
[patent_app_number] => 8/957044
[patent_app_country] => US
[patent_app_date] => 1997-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3939
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/012/06012104.pdf
[firstpage_image] =>[orig_patent_app_number] => 957044
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/957044 | Method and apparatus for dynamic extension of channel programs | Oct 23, 1997 | Issued |
Array
(
[id] => 4239979
[patent_doc_number] => 06012118
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus'
[patent_app_type] => 1
[patent_app_number] => 8/954442
[patent_app_country] => US
[patent_app_date] => 1997-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 11199
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/012/06012118.pdf
[firstpage_image] =>[orig_patent_app_number] => 954442
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/954442 | Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus | Oct 19, 1997 | Issued |
Array
(
[id] => 4403668
[patent_doc_number] => 06263385
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'PC parallel port structure partitioned between two integrated circuits interconnected by a serial bus'
[patent_app_type] => 1
[patent_app_number] => 8/955327
[patent_app_country] => US
[patent_app_date] => 1997-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 29
[patent_no_of_words] => 9578
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/263/06263385.pdf
[firstpage_image] =>[orig_patent_app_number] => 955327
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/955327 | PC parallel port structure partitioned between two integrated circuits interconnected by a serial bus | Oct 19, 1997 | Issued |