Search

Rupal Dharia

Supervisory Patent Examiner (ID: 11240, Phone: (571)272-3880 , Office: P/2400 )

Most Active Art Unit
2181
Art Unit(s)
2305, 2456, 2441, 2100, 2400, 2443, 2181, 2492, 2189, 2781, 2141
Total Applications
411
Issued Applications
349
Pending Applications
24
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4152199 [patent_doc_number] => 06148352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Scalable modular data storage system' [patent_app_type] => 1 [patent_app_number] => 8/997962 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4721 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148352.pdf [firstpage_image] =>[orig_patent_app_number] => 997962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997962
Scalable modular data storage system Dec 23, 1997 Issued
Array ( [id] => 4101010 [patent_doc_number] => 06163827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method and apparatus for round-robin flash channel arbitration' [patent_app_type] => 1 [patent_app_number] => 8/991254 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1851 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163827.pdf [firstpage_image] =>[orig_patent_app_number] => 991254 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991254
Method and apparatus for round-robin flash channel arbitration Dec 15, 1997 Issued
Array ( [id] => 1431399 [patent_doc_number] => 06523129 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method of preventing computer malfunction during a change of power consumption states via dynamic adjustment of core voltage' [patent_app_type] => B1 [patent_app_number] => 08/991107 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523129.pdf [firstpage_image] =>[orig_patent_app_number] => 08991107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991107
Method of preventing computer malfunction during a change of power consumption states via dynamic adjustment of core voltage Dec 15, 1997 Issued
Array ( [id] => 4373858 [patent_doc_number] => 06292860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for preventing deadlock by suspending operation of processors, bridges, and devices' [patent_app_type] => 1 [patent_app_number] => 8/991697 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2641 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292860.pdf [firstpage_image] =>[orig_patent_app_number] => 991697 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991697
Method for preventing deadlock by suspending operation of processors, bridges, and devices Dec 15, 1997 Issued
Array ( [id] => 4374538 [patent_doc_number] => 06170032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Priority encoder circuit' [patent_app_type] => 1 [patent_app_number] => 8/990478 [patent_app_country] => US [patent_app_date] => 1997-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4615 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170032.pdf [firstpage_image] =>[orig_patent_app_number] => 990478 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/990478
Priority encoder circuit Dec 14, 1997 Issued
Array ( [id] => 4376251 [patent_doc_number] => 06219741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Transactions supporting interrupt destination redirection and level triggered interrupt semantics' [patent_app_type] => 1 [patent_app_number] => 8/988232 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6914 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219741.pdf [firstpage_image] =>[orig_patent_app_number] => 988232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988232
Transactions supporting interrupt destination redirection and level triggered interrupt semantics Dec 9, 1997 Issued
Array ( [id] => 4334967 [patent_doc_number] => 06243780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Interface of a monitor communicating with personal computer' [patent_app_type] => 1 [patent_app_number] => 8/979118 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2781 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243780.pdf [firstpage_image] =>[orig_patent_app_number] => 979118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979118
Interface of a monitor communicating with personal computer Nov 25, 1997 Issued
Array ( [id] => 4198642 [patent_doc_number] => 06038613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Prefetching and storing device work information from multiple data storage devices' [patent_app_type] => 1 [patent_app_number] => 8/971085 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5222 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038613.pdf [firstpage_image] =>[orig_patent_app_number] => 971085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971085
Prefetching and storing device work information from multiple data storage devices Nov 13, 1997 Issued
08/962624 AUTOMATIC BACKUP BASED ON DISK DRIVE CONDITION Nov 2, 1997 Abandoned
Array ( [id] => 3802384 [patent_doc_number] => 05822545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Method and apparatus for eliminating electromagnetic interference and noise caused by all unnecessary switching/toggling of bus signals' [patent_app_type] => 1 [patent_app_number] => 8/960585 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3329 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822545.pdf [firstpage_image] =>[orig_patent_app_number] => 960585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960585
Method and apparatus for eliminating electromagnetic interference and noise caused by all unnecessary switching/toggling of bus signals Oct 28, 1997 Issued
Array ( [id] => 4109546 [patent_doc_number] => 06134604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Communication apparatus for communicating with a plurality of communication control units cascade-connected' [patent_app_type] => 1 [patent_app_number] => 8/958561 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 4972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134604.pdf [firstpage_image] =>[orig_patent_app_number] => 958561 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958561
Communication apparatus for communicating with a plurality of communication control units cascade-connected Oct 26, 1997 Issued
Array ( [id] => 4239789 [patent_doc_number] => 06012104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method and apparatus for dynamic extension of channel programs' [patent_app_type] => 1 [patent_app_number] => 8/957044 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3939 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012104.pdf [firstpage_image] =>[orig_patent_app_number] => 957044 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957044
Method and apparatus for dynamic extension of channel programs Oct 23, 1997 Issued
Array ( [id] => 4403668 [patent_doc_number] => 06263385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'PC parallel port structure partitioned between two integrated circuits interconnected by a serial bus' [patent_app_type] => 1 [patent_app_number] => 8/955327 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 9578 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263385.pdf [firstpage_image] =>[orig_patent_app_number] => 955327 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955327
PC parallel port structure partitioned between two integrated circuits interconnected by a serial bus Oct 19, 1997 Issued
Array ( [id] => 4239979 [patent_doc_number] => 06012118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus' [patent_app_type] => 1 [patent_app_number] => 8/954442 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11199 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012118.pdf [firstpage_image] =>[orig_patent_app_number] => 954442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954442
Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus Oct 19, 1997 Issued
Array ( [id] => 1429492 [patent_doc_number] => 06530026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Circuit and method for power distribution management' [patent_app_type] => B1 [patent_app_number] => 08/954334 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530026.pdf [firstpage_image] =>[orig_patent_app_number] => 08954334 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954334
Circuit and method for power distribution management Oct 16, 1997 Issued
Array ( [id] => 1592262 [patent_doc_number] => 06360288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method and modules for control of pipelines carrying data using pipelines carrying control signals' [patent_app_type] => B1 [patent_app_number] => 08/953767 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 10075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360288.pdf [firstpage_image] =>[orig_patent_app_number] => 08953767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953767
Method and modules for control of pipelines carrying data using pipelines carrying control signals Oct 16, 1997 Issued
Array ( [id] => 4426603 [patent_doc_number] => 06178477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource' [patent_app_type] => 1 [patent_app_number] => 8/947650 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5541 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178477.pdf [firstpage_image] =>[orig_patent_app_number] => 947650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/947650
Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource Oct 8, 1997 Issued
Array ( [id] => 4336941 [patent_doc_number] => 06249834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'System for expanding PCI bus loading capacity' [patent_app_type] => 1 [patent_app_number] => 8/942404 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3869 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249834.pdf [firstpage_image] =>[orig_patent_app_number] => 942404 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942404
System for expanding PCI bus loading capacity Sep 30, 1997 Issued
Array ( [id] => 4036639 [patent_doc_number] => 05968147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method and apparatus for improved peripheral bus utilization' [patent_app_type] => 1 [patent_app_number] => 8/938110 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8341 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968147.pdf [firstpage_image] =>[orig_patent_app_number] => 938110 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938110
Method and apparatus for improved peripheral bus utilization Sep 25, 1997 Issued
Array ( [id] => 4115982 [patent_doc_number] => 06067594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'High frequency bus system' [patent_app_type] => 1 [patent_app_number] => 8/938084 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 7854 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067594.pdf [firstpage_image] =>[orig_patent_app_number] => 938084 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938084
High frequency bus system Sep 25, 1997 Issued
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