Search

Rupal Dharia

Supervisory Patent Examiner (ID: 10979, Phone: (571)272-3880 , Office: P/2400 )

Most Active Art Unit
2181
Art Unit(s)
2781, 2189, 2441, 2456, 2492, 2400, 2181, 2305, 2141, 2100, 2443
Total Applications
411
Issued Applications
349
Pending Applications
24
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
08/813529 METHOD AND APPARATUS FOR INCREASING DATA THROUGHPUT IN A COMPUTER SYSTEM BY SELECTION OF DATA PATHS Mar 6, 1997 Abandoned
Array ( [id] => 4030976 [patent_doc_number] => 05881248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'System and method for optimizing system bus bandwidth in an embedded communication system' [patent_app_type] => 1 [patent_app_number] => 8/812218 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6234 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881248.pdf [firstpage_image] =>[orig_patent_app_number] => 812218 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812218
System and method for optimizing system bus bandwidth in an embedded communication system Mar 5, 1997 Issued
Array ( [id] => 4008205 [patent_doc_number] => 05892931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and apparatus for splitting a bus target response between two devices in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/810690 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4994 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892931.pdf [firstpage_image] =>[orig_patent_app_number] => 810690 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/810690
Method and apparatus for splitting a bus target response between two devices in a computer system Feb 27, 1997 Issued
Array ( [id] => 4100948 [patent_doc_number] => 06163823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Dynamic addressing of devices on a shared medium network with a keyline' [patent_app_type] => 1 [patent_app_number] => 8/791754 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3994 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163823.pdf [firstpage_image] =>[orig_patent_app_number] => 791754 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/791754
Dynamic addressing of devices on a shared medium network with a keyline Jan 28, 1997 Issued
Array ( [id] => 4299373 [patent_doc_number] => 06282663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method and apparatus for performing power management by suppressing the speculative execution of instructions within a pipelined microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/787549 [patent_app_country] => US [patent_app_date] => 1997-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6799 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282663.pdf [firstpage_image] =>[orig_patent_app_number] => 787549 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/787549
Method and apparatus for performing power management by suppressing the speculative execution of instructions within a pipelined microprocessor Jan 21, 1997 Issued
Array ( [id] => 4057923 [patent_doc_number] => 05996084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and apparatus for real-time CPU thermal management and power conservation by adjusting CPU clock frequency in accordance with CPU activity' [patent_app_type] => 1 [patent_app_number] => 8/785619 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 10758 [patent_no_of_claims] => 90 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996084.pdf [firstpage_image] =>[orig_patent_app_number] => 785619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785619
Method and apparatus for real-time CPU thermal management and power conservation by adjusting CPU clock frequency in accordance with CPU activity Jan 16, 1997 Issued
Array ( [id] => 4225682 [patent_doc_number] => 06029222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method and processor for selectively marking instructions as interruptible or uninterruptible and judging interrupt requests based on the marked instruction' [patent_app_type] => 1 [patent_app_number] => 8/781718 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2936 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029222.pdf [firstpage_image] =>[orig_patent_app_number] => 781718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781718
Method and processor for selectively marking instructions as interruptible or uninterruptible and judging interrupt requests based on the marked instruction Jan 9, 1997 Issued
Array ( [id] => 4023843 [patent_doc_number] => 05890002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'System and method for bus master emulation' [patent_app_type] => 1 [patent_app_number] => 8/775174 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4896 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890002.pdf [firstpage_image] =>[orig_patent_app_number] => 775174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775174
System and method for bus master emulation Dec 30, 1996 Issued
08/774512 METHOD AND APPARATUS FOR ZERO LATENCY BUS TRANSACTIONS Dec 29, 1996 Abandoned
Array ( [id] => 4023869 [patent_doc_number] => 05890004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Method and apparatus for signaling power management events between two devices' [patent_app_type] => 1 [patent_app_number] => 8/777550 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3414 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890004.pdf [firstpage_image] =>[orig_patent_app_number] => 777550 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777550
Method and apparatus for signaling power management events between two devices Dec 29, 1996 Issued
Array ( [id] => 3783032 [patent_doc_number] => 05850556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Interruptible state machine' [patent_app_type] => 1 [patent_app_number] => 8/780167 [patent_app_country] => US [patent_app_date] => 1996-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 10365 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850556.pdf [firstpage_image] =>[orig_patent_app_number] => 780167 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780167
Interruptible state machine Dec 25, 1996 Issued
Array ( [id] => 3962252 [patent_doc_number] => 05974552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method and apparatus for executing a scheduled operation after wake up from power off state' [patent_app_type] => 1 [patent_app_number] => 8/773718 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3951 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974552.pdf [firstpage_image] =>[orig_patent_app_number] => 773718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773718
Method and apparatus for executing a scheduled operation after wake up from power off state Dec 22, 1996 Issued
Array ( [id] => 4222434 [patent_doc_number] => 06029006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Data processor with circuit for regulating instruction throughput while powered and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/772713 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 9999 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029006.pdf [firstpage_image] =>[orig_patent_app_number] => 772713 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/772713
Data processor with circuit for regulating instruction throughput while powered and method of operation Dec 22, 1996 Issued
Array ( [id] => 4171824 [patent_doc_number] => 06125450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Stop clock throttling in a computer processor through disabling bus masters' [patent_app_type] => 1 [patent_app_number] => 8/770715 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125450.pdf [firstpage_image] =>[orig_patent_app_number] => 770715 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770715
Stop clock throttling in a computer processor through disabling bus masters Dec 18, 1996 Issued
Array ( [id] => 3961264 [patent_doc_number] => 05974489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Computer bus expansion' [patent_app_type] => 1 [patent_app_number] => 8/769146 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4893 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974489.pdf [firstpage_image] =>[orig_patent_app_number] => 769146 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769146
Computer bus expansion Dec 17, 1996 Issued
Array ( [id] => 4101156 [patent_doc_number] => 06018803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method and apparatus for detecting bus utilization in a computer system based on a number of bus events per sample period' [patent_app_type] => 1 [patent_app_number] => 8/768913 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5183 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018803.pdf [firstpage_image] =>[orig_patent_app_number] => 768913 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768913
Method and apparatus for detecting bus utilization in a computer system based on a number of bus events per sample period Dec 16, 1996 Issued
Array ( [id] => 3745484 [patent_doc_number] => 05694584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Information processing system capable of quickly processing a parameter and a command necessary for drawing processing' [patent_app_type] => 1 [patent_app_number] => 8/761864 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7269 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694584.pdf [firstpage_image] =>[orig_patent_app_number] => 761864 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761864
Information processing system capable of quickly processing a parameter and a command necessary for drawing processing Dec 8, 1996 Issued
Array ( [id] => 3974239 [patent_doc_number] => 05901296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Distributed scheduling for the transfer of real time, loss sensitive and non-real time data over a bus' [patent_app_type] => 1 [patent_app_number] => 8/760914 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3536 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901296.pdf [firstpage_image] =>[orig_patent_app_number] => 760914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760914
Distributed scheduling for the transfer of real time, loss sensitive and non-real time data over a bus Dec 5, 1996 Issued
Array ( [id] => 3997465 [patent_doc_number] => 05961648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Heater preheating device for cathode ray tube' [patent_app_type] => 1 [patent_app_number] => 8/764070 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5598 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961648.pdf [firstpage_image] =>[orig_patent_app_number] => 764070 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/764070
Heater preheating device for cathode ray tube Dec 5, 1996 Issued
Array ( [id] => 4023360 [patent_doc_number] => 05889969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Logical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structure' [patent_app_type] => 1 [patent_app_number] => 8/737951 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6272 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889969.pdf [firstpage_image] =>[orig_patent_app_number] => 737951 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/737951
Logical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structure Nov 26, 1996 Issued
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