
Rupal Dharia
Supervisory Patent Examiner (ID: 2589, Phone: (571)272-3880 , Office: P/2400 )
| Most Active Art Unit | 2181 |
| Art Unit(s) | 2181, 2781, 2492, 2305, 2400, 2100, 2456, 2141, 2189, 2443, 2441 |
| Total Applications | 412 |
| Issued Applications | 349 |
| Pending Applications | 25 |
| Abandoned Applications | 39 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3794086
[patent_doc_number] => 05809262
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Commonly housed multiple processor type computing system and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/706001
[patent_app_country] => US
[patent_app_date] => 1996-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5346
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/809/05809262.pdf
[firstpage_image] =>[orig_patent_app_number] => 706001
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/706001 | Commonly housed multiple processor type computing system and method of manufacturing the same | Aug 29, 1996 | Issued |
Array
(
[id] => 4047701
[patent_doc_number] => 05857081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'Method and apparatus for controlling a master abort in a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/706351
[patent_app_country] => US
[patent_app_date] => 1996-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7865
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/857/05857081.pdf
[firstpage_image] =>[orig_patent_app_number] => 706351
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/706351 | Method and apparatus for controlling a master abort in a computer system | Aug 29, 1996 | Issued |
Array
(
[id] => 3997096
[patent_doc_number] => 05961623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system'
[patent_app_type] => 1
[patent_app_number] => 8/705324
[patent_app_country] => US
[patent_app_date] => 1996-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 62
[patent_no_of_words] => 15231
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/961/05961623.pdf
[firstpage_image] =>[orig_patent_app_number] => 705324
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/705324 | Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system | Aug 28, 1996 | Issued |
Array
(
[id] => 4057975
[patent_doc_number] => 05913068
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Multi-processor power saving system which dynamically detects the necessity of a power saving operation to control the parallel degree of a plurality of processors'
[patent_app_type] => 1
[patent_app_number] => 8/704078
[patent_app_country] => US
[patent_app_date] => 1996-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6505
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/913/05913068.pdf
[firstpage_image] =>[orig_patent_app_number] => 704078
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/704078 | Multi-processor power saving system which dynamically detects the necessity of a power saving operation to control the parallel degree of a plurality of processors | Aug 27, 1996 | Issued |
Array
(
[id] => 3894644
[patent_doc_number] => 05826047
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Method and apparatus for external viewing of an internal bus'
[patent_app_type] => 1
[patent_app_number] => 8/703252
[patent_app_country] => US
[patent_app_date] => 1996-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2617
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/826/05826047.pdf
[firstpage_image] =>[orig_patent_app_number] => 703252
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/703252 | Method and apparatus for external viewing of an internal bus | Aug 25, 1996 | Issued |
Array
(
[id] => 4421913
[patent_doc_number] => 06233634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-15
[patent_title] => 'Server controller configured to snoop and receive a duplicative copy of display data presented to a video controller'
[patent_app_type] => 1
[patent_app_number] => 8/697678
[patent_app_country] => US
[patent_app_date] => 1996-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 15993
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/233/06233634.pdf
[firstpage_image] =>[orig_patent_app_number] => 697678
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/697678 | Server controller configured to snoop and receive a duplicative copy of display data presented to a video controller | Aug 16, 1996 | Issued |
Array
(
[id] => 3932738
[patent_doc_number] => 06003108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Method and system for interrupt-responsive execution of communications protocols'
[patent_app_type] => 1
[patent_app_number] => 8/695741
[patent_app_country] => US
[patent_app_date] => 1996-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6114
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/003/06003108.pdf
[firstpage_image] =>[orig_patent_app_number] => 695741
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/695741 | Method and system for interrupt-responsive execution of communications protocols | Aug 11, 1996 | Issued |
Array
(
[id] => 3787989
[patent_doc_number] => 05774681
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Method and apparatus for controlling a response timing of a target ready signal on a PCI bridge'
[patent_app_type] => 1
[patent_app_number] => 8/694676
[patent_app_country] => US
[patent_app_date] => 1996-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8965
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774681.pdf
[firstpage_image] =>[orig_patent_app_number] => 694676
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/694676 | Method and apparatus for controlling a response timing of a target ready signal on a PCI bridge | Aug 8, 1996 | Issued |
Array
(
[id] => 4064742
[patent_doc_number] => 05870571
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Automatic control of data transfer rates over a computer bus'
[patent_app_type] => 1
[patent_app_number] => 8/691777
[patent_app_country] => US
[patent_app_date] => 1996-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2878
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/870/05870571.pdf
[firstpage_image] =>[orig_patent_app_number] => 691777
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/691777 | Automatic control of data transfer rates over a computer bus | Aug 1, 1996 | Issued |
Array
(
[id] => 3894279
[patent_doc_number] => 05729749
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Exclusive control system for shared resource'
[patent_app_type] => 1
[patent_app_number] => 8/684907
[patent_app_country] => US
[patent_app_date] => 1996-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9776
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/729/05729749.pdf
[firstpage_image] =>[orig_patent_app_number] => 684907
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/684907 | Exclusive control system for shared resource | Jul 24, 1996 | Issued |
Array
(
[id] => 3857874
[patent_doc_number] => 05848281
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Method and apparatus for powder management in a multifunction controller with an embedded microprocessor'
[patent_app_type] => 1
[patent_app_number] => 8/685378
[patent_app_country] => US
[patent_app_date] => 1996-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5328
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/848/05848281.pdf
[firstpage_image] =>[orig_patent_app_number] => 685378
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/685378 | Method and apparatus for powder management in a multifunction controller with an embedded microprocessor | Jul 22, 1996 | Issued |
Array
(
[id] => 4178395
[patent_doc_number] => 06115748
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Prioritized access to shared buffers'
[patent_app_type] => 1
[patent_app_number] => 8/683448
[patent_app_country] => US
[patent_app_date] => 1996-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 28
[patent_no_of_words] => 11189
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/115/06115748.pdf
[firstpage_image] =>[orig_patent_app_number] => 683448
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/683448 | Prioritized access to shared buffers | Jul 17, 1996 | Issued |
Array
(
[id] => 4038361
[patent_doc_number] => 05911777
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Method and apparatus for reporting unauthorized attempt to release a portable computer from a docking station'
[patent_app_type] => 1
[patent_app_number] => 8/675952
[patent_app_country] => US
[patent_app_date] => 1996-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 3011
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/911/05911777.pdf
[firstpage_image] =>[orig_patent_app_number] => 675952
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/675952 | Method and apparatus for reporting unauthorized attempt to release a portable computer from a docking station | Jul 4, 1996 | Issued |
Array
(
[id] => 3893979
[patent_doc_number] => 05764934
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Processor subsystem for use with a universal computer architecture'
[patent_app_type] => 1
[patent_app_number] => 8/675854
[patent_app_country] => US
[patent_app_date] => 1996-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6757
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764934.pdf
[firstpage_image] =>[orig_patent_app_number] => 675854
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/675854 | Processor subsystem for use with a universal computer architecture | Jul 2, 1996 | Issued |
Array
(
[id] => 3872200
[patent_doc_number] => 05768549
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Input interface using multiplex type input circuit'
[patent_app_type] => 1
[patent_app_number] => 8/673045
[patent_app_country] => US
[patent_app_date] => 1996-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 4804
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/768/05768549.pdf
[firstpage_image] =>[orig_patent_app_number] => 673045
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/673045 | Input interface using multiplex type input circuit | Jun 30, 1996 | Issued |
Array
(
[id] => 3923849
[patent_doc_number] => 05938750
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Method and apparatus for a memory card bus design'
[patent_app_type] => 1
[patent_app_number] => 8/672827
[patent_app_country] => US
[patent_app_date] => 1996-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4131
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/938/05938750.pdf
[firstpage_image] =>[orig_patent_app_number] => 672827
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/672827 | Method and apparatus for a memory card bus design | Jun 27, 1996 | Issued |
Array
(
[id] => 3970410
[patent_doc_number] => 05958059
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Data processing apparatus connectable to an information processing terminal via an interface'
[patent_app_type] => 1
[patent_app_number] => 8/662948
[patent_app_country] => US
[patent_app_date] => 1996-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4336
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/958/05958059.pdf
[firstpage_image] =>[orig_patent_app_number] => 662948
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/662948 | Data processing apparatus connectable to an information processing terminal via an interface | Jun 12, 1996 | Issued |
Array
(
[id] => 4047727
[patent_doc_number] => 05857083
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'Bus interfacing device for interfacing a secondary peripheral bus with a system having a host CPU and a primary peripheral bus'
[patent_app_type] => 1
[patent_app_number] => 8/663006
[patent_app_country] => US
[patent_app_date] => 1996-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 8718
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/857/05857083.pdf
[firstpage_image] =>[orig_patent_app_number] => 663006
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/663006 | Bus interfacing device for interfacing a secondary peripheral bus with a system having a host CPU and a primary peripheral bus | Jun 6, 1996 | Issued |
Array
(
[id] => 4177527
[patent_doc_number] => 06108741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Ordering transactions'
[patent_app_type] => 1
[patent_app_number] => 8/655254
[patent_app_country] => US
[patent_app_date] => 1996-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 127
[patent_figures_cnt] => 129
[patent_no_of_words] => 71170
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/108/06108741.pdf
[firstpage_image] =>[orig_patent_app_number] => 655254
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/655254 | Ordering transactions | Jun 4, 1996 | Issued |
Array
(
[id] => 3842201
[patent_doc_number] => 05784623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Using a parent latch that covers a plurality of child latches to track the progress of a process attempting to acquire resources'
[patent_app_type] => 1
[patent_app_number] => 8/654552
[patent_app_country] => US
[patent_app_date] => 1996-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3770
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/784/05784623.pdf
[firstpage_image] =>[orig_patent_app_number] => 654552
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/654552 | Using a parent latch that covers a plurality of child latches to track the progress of a process attempting to acquire resources | May 28, 1996 | Issued |