Search

Rupal Dharia

Supervisory Patent Examiner (ID: 14113, Phone: (571)272-3880 , Office: P/2400 )

Most Active Art Unit
2181
Art Unit(s)
2400, 2492, 2189, 2443, 2781, 2181, 2305, 2456, 2100, 2441, 2141
Total Applications
417
Issued Applications
349
Pending Applications
30
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3923849 [patent_doc_number] => 05938750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method and apparatus for a memory card bus design' [patent_app_type] => 1 [patent_app_number] => 8/672827 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4131 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938750.pdf [firstpage_image] =>[orig_patent_app_number] => 672827 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672827
Method and apparatus for a memory card bus design Jun 27, 1996 Issued
Array ( [id] => 3970410 [patent_doc_number] => 05958059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Data processing apparatus connectable to an information processing terminal via an interface' [patent_app_type] => 1 [patent_app_number] => 8/662948 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4336 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958059.pdf [firstpage_image] =>[orig_patent_app_number] => 662948 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662948
Data processing apparatus connectable to an information processing terminal via an interface Jun 12, 1996 Issued
Array ( [id] => 4047727 [patent_doc_number] => 05857083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Bus interfacing device for interfacing a secondary peripheral bus with a system having a host CPU and a primary peripheral bus' [patent_app_type] => 1 [patent_app_number] => 8/663006 [patent_app_country] => US [patent_app_date] => 1996-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8718 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/857/05857083.pdf [firstpage_image] =>[orig_patent_app_number] => 663006 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663006
Bus interfacing device for interfacing a secondary peripheral bus with a system having a host CPU and a primary peripheral bus Jun 6, 1996 Issued
Array ( [id] => 4177527 [patent_doc_number] => 06108741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Ordering transactions' [patent_app_type] => 1 [patent_app_number] => 8/655254 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 127 [patent_figures_cnt] => 129 [patent_no_of_words] => 71170 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108741.pdf [firstpage_image] =>[orig_patent_app_number] => 655254 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655254
Ordering transactions Jun 4, 1996 Issued
Array ( [id] => 3842201 [patent_doc_number] => 05784623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Using a parent latch that covers a plurality of child latches to track the progress of a process attempting to acquire resources' [patent_app_type] => 1 [patent_app_number] => 8/654552 [patent_app_country] => US [patent_app_date] => 1996-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3770 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784623.pdf [firstpage_image] =>[orig_patent_app_number] => 654552 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654552
Using a parent latch that covers a plurality of child latches to track the progress of a process attempting to acquire resources May 28, 1996 Issued
Array ( [id] => 3859146 [patent_doc_number] => 05745769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Multiple connection method using a single control link' [patent_app_type] => 1 [patent_app_number] => 8/653478 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3149 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745769.pdf [firstpage_image] =>[orig_patent_app_number] => 653478 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653478
Multiple connection method using a single control link May 23, 1996 Issued
Array ( [id] => 3993170 [patent_doc_number] => 05918056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Segmentation suspend mode for real-time interrupt support' [patent_app_type] => 1 [patent_app_number] => 8/649246 [patent_app_country] => US [patent_app_date] => 1996-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2339 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918056.pdf [firstpage_image] =>[orig_patent_app_number] => 649246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649246
Segmentation suspend mode for real-time interrupt support May 16, 1996 Issued
Array ( [id] => 4085017 [patent_doc_number] => 06009485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Information processing apparatus and method, and storage medium storing control programs' [patent_app_type] => 1 [patent_app_number] => 8/649075 [patent_app_country] => US [patent_app_date] => 1996-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4452 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009485.pdf [firstpage_image] =>[orig_patent_app_number] => 649075 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649075
Information processing apparatus and method, and storage medium storing control programs May 15, 1996 Issued
Array ( [id] => 3899045 [patent_doc_number] => 05748969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Arbitration apparatus using least recently used algorithm' [patent_app_type] => 1 [patent_app_number] => 8/649134 [patent_app_country] => US [patent_app_date] => 1996-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3853 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748969.pdf [firstpage_image] =>[orig_patent_app_number] => 649134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649134
Arbitration apparatus using least recently used algorithm May 13, 1996 Issued
Array ( [id] => 3641864 [patent_doc_number] => 05687325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Application specific field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 8/634728 [patent_app_country] => US [patent_app_date] => 1996-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4920 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687325.pdf [firstpage_image] =>[orig_patent_app_number] => 634728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634728
Application specific field programmable gate array Apr 18, 1996 Issued
Array ( [id] => 3756062 [patent_doc_number] => 05787292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Power saving method and apparatus for use in multiple frequency zone drives' [patent_app_type] => 1 [patent_app_number] => 8/625334 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 9 [patent_no_of_words] => 9502 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787292.pdf [firstpage_image] =>[orig_patent_app_number] => 625334 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/625334
Power saving method and apparatus for use in multiple frequency zone drives Mar 31, 1996 Issued
Array ( [id] => 3893919 [patent_doc_number] => 05764930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus for providing reset transparency on a reconfigurable bus' [patent_app_type] => 1 [patent_app_number] => 8/626129 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4589 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764930.pdf [firstpage_image] =>[orig_patent_app_number] => 626129 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626129
Method and apparatus for providing reset transparency on a reconfigurable bus Mar 31, 1996 Issued
Array ( [id] => 4316199 [patent_doc_number] => 06199133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Management communication bus for networking devices' [patent_app_type] => 1 [patent_app_number] => 8/624176 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9647 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199133.pdf [firstpage_image] =>[orig_patent_app_number] => 624176 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/624176
Management communication bus for networking devices Mar 28, 1996 Issued
Array ( [id] => 3850134 [patent_doc_number] => 05815724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Method and apparatus for controlling power consumption in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/623978 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3639 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815724.pdf [firstpage_image] =>[orig_patent_app_number] => 623978 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623978
Method and apparatus for controlling power consumption in a microprocessor Mar 28, 1996 Issued
Array ( [id] => 3847800 [patent_doc_number] => 05740382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method and apparatus for accessing a chip-selectable device in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/623482 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 15736 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740382.pdf [firstpage_image] =>[orig_patent_app_number] => 623482 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/623482
Method and apparatus for accessing a chip-selectable device in a data processing system Mar 27, 1996 Issued
Array ( [id] => 3919434 [patent_doc_number] => 05752049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Integrated computer and printer system and method for managing power source therefor' [patent_app_type] => 1 [patent_app_number] => 8/621183 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6034 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752049.pdf [firstpage_image] =>[orig_patent_app_number] => 621183 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/621183
Integrated computer and printer system and method for managing power source therefor Mar 20, 1996 Issued
Array ( [id] => 4031014 [patent_doc_number] => 05881250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Host adapter system including an integrated PCI buffer controller and XOR function circuit' [patent_app_type] => 1 [patent_app_number] => 8/615477 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10842 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881250.pdf [firstpage_image] =>[orig_patent_app_number] => 615477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/615477
Host adapter system including an integrated PCI buffer controller and XOR function circuit Mar 14, 1996 Issued
Array ( [id] => 3955139 [patent_doc_number] => 05930487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'PCI bus master with cascaded PCI arbitration' [patent_app_type] => 1 [patent_app_number] => 8/611784 [patent_app_country] => US [patent_app_date] => 1996-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3539 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930487.pdf [firstpage_image] =>[orig_patent_app_number] => 611784 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/611784
PCI bus master with cascaded PCI arbitration Mar 5, 1996 Issued
Array ( [id] => 3741418 [patent_doc_number] => 05671368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'PC card controller circuit to detect exchange of PC cards while in suspend mode' [patent_app_type] => 1 [patent_app_number] => 8/605752 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5810 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671368.pdf [firstpage_image] =>[orig_patent_app_number] => 605752 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605752
PC card controller circuit to detect exchange of PC cards while in suspend mode Feb 21, 1996 Issued
Array ( [id] => 3830814 [patent_doc_number] => 05812860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control power consumption' [patent_app_type] => 1 [patent_app_number] => 8/599648 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2513 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812860.pdf [firstpage_image] =>[orig_patent_app_number] => 599648 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/599648
Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control power consumption Feb 11, 1996 Issued
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