Rupal Dharia

Array ( [id] => 3717186 [patent_doc_number] => 05675814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Apparatus and method for managing power consumption by I/O ports in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/591850 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4773 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675814.pdf [firstpage_image] =>[orig_patent_app_number] => 591850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602202 [patent_doc_number] => 06493782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method for performing hot docking of a portable computer into a docking station' [patent_app_type] => B1 [patent_app_number] => 08/587176 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7338 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493782.pdf [firstpage_image] =>[orig_patent_app_number] => 08587176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3794010 [patent_doc_number] => 05809257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Bus control apparatus for data transfer system' [patent_app_type] => 1 [patent_app_number] => 8/584548 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 8191 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809257.pdf [firstpage_image] =>[orig_patent_app_number] => 584548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3919135 [patent_doc_number] => 05898879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Power consumption reducing apparatus in using no CPU bus system and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/581369 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1354 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898879.pdf [firstpage_image] =>[orig_patent_app_number] => 581369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3917921 [patent_doc_number] => 05913924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Use of a stored signal to switch between memory banks' [patent_app_type] => 1 [patent_app_number] => 8/574534 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5385 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913924.pdf [firstpage_image] =>[orig_patent_app_number] => 574534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4126612 [patent_doc_number] => 06058448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Circuit for preventing bus contention' [patent_app_type] => 1 [patent_app_number] => 8/574771 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4237 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058448.pdf [firstpage_image] =>[orig_patent_app_number] => 574771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3824716 [patent_doc_number] => 05710890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Method and device for the transmission of data on a bus' [patent_app_type] => 1 [patent_app_number] => 8/573853 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5335 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710890.pdf [firstpage_image] =>[orig_patent_app_number] => 573853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3788802 [patent_doc_number] => 05774736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Redundant CPU power system' [patent_app_type] => 1 [patent_app_number] => 8/572794 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 15229 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774736.pdf [firstpage_image] =>[orig_patent_app_number] => 572794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3734471 [patent_doc_number] => 05682509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Bus interface to a RAID architecture' [patent_app_type] => 1 [patent_app_number] => 8/571386 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7928 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682509.pdf [firstpage_image] =>[orig_patent_app_number] => 571386 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1068373 [patent_doc_number] => 06848054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-25 [patent_title] => 'Real-time computer thermal management and power conservation' [patent_app_type] => utility [patent_app_number] => 08/572202 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 12014 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/848/06848054.pdf [firstpage_image] =>[orig_patent_app_number] => 08572202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3785327 [patent_doc_number] => 05734911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Method of linking peripheral devices all of which use the same IRQ to a single interrupt procedure' [patent_app_type] => 1 [patent_app_number] => 8/569601 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4252 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734911.pdf [firstpage_image] =>[orig_patent_app_number] => 569601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3700921 [patent_doc_number] => 05664125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'PCMCIA interface system with adjacently aligned cable to prevent crosstalk' [patent_app_type] => 1 [patent_app_number] => 8/567889 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 3836 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664125.pdf [firstpage_image] =>[orig_patent_app_number] => 567889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4081979 [patent_doc_number] => 05867718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method and apparatus for waking up a computer system via a parallel port' [patent_app_type] => 1 [patent_app_number] => 8/564952 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2262 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867718.pdf [firstpage_image] =>[orig_patent_app_number] => 564952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3755582 [patent_doc_number] => 05787261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Data transfer system, computer system and active-line inserted/withdrawn functional circuit board' [patent_app_type] => 1 [patent_app_number] => 8/563106 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10215 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787261.pdf [firstpage_image] =>[orig_patent_app_number] => 563106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3966917 [patent_doc_number] => 05983298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Industrial controller permitting removal and insertion of circuit cards while under power' [patent_app_type] => 1 [patent_app_number] => 8/561506 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 8315 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983298.pdf [firstpage_image] =>[orig_patent_app_number] => 561506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3918278 [patent_doc_number] => 05751978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Multi-purpose peripheral bus driver apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/557401 [patent_app_country] => US [patent_app_date] => 1995-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6586 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751978.pdf [firstpage_image] =>[orig_patent_app_number] => 557401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3803267 [patent_doc_number] => 05822596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Controlling power up using clock gating' [patent_app_type] => 1 [patent_app_number] => 8/554206 [patent_app_country] => US [patent_app_date] => 1995-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4306 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822596.pdf [firstpage_image] =>[orig_patent_app_number] => 554206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3677453 [patent_doc_number] => 05668957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Method and apparatus for providing virtual DMA capability on an adapter connected to a computer system bus with no DMA support' [patent_app_type] => 1 [patent_app_number] => 8/556773 [patent_app_country] => US [patent_app_date] => 1995-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3734 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668957.pdf [firstpage_image] =>[orig_patent_app_number] => 556773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381048 [patent_doc_number] => 06256696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Information processing system comprising at least two processors' [patent_app_type] => 1 [patent_app_number] => 8/548113 [patent_app_country] => US [patent_app_date] => 1995-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5086 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256696.pdf [firstpage_image] =>[orig_patent_app_number] => 548113 [rel_patent_id] =>[rel_patent_doc_number] =>)