Search

Rupal Dharia

Supervisory Patent Examiner (ID: 12531, Phone: (571)272-3880 , Office: P/2400 )

Most Active Art Unit
2181
Art Unit(s)
2181, 2400, 2100, 2456, 2443, 2141, 2441, 2781, 2189, 2305, 2492
Total Applications
411
Issued Applications
349
Pending Applications
24
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7645928 [patent_doc_number] => 06477595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Scalable DSL access multiplexer with high reliability' [patent_app_type] => B1 [patent_app_number] => 09/547921 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8402 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477595.pdf [firstpage_image] =>[orig_patent_app_number] => 09547921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/547921
Scalable DSL access multiplexer with high reliability Apr 10, 2000 Issued
Array ( [id] => 7611358 [patent_doc_number] => 06904484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-07 [patent_title] => 'Low pin count (LPC) firmware hub recovery' [patent_app_type] => utility [patent_app_number] => 09/539517 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2002 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904484.pdf [firstpage_image] =>[orig_patent_app_number] => 09539517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539517
Low pin count (LPC) firmware hub recovery Mar 29, 2000 Issued
Array ( [id] => 1395058 [patent_doc_number] => 06567874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Signal switch apparatus' [patent_app_type] => B1 [patent_app_number] => 09/536778 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1865 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567874.pdf [firstpage_image] =>[orig_patent_app_number] => 09536778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536778
Signal switch apparatus Mar 27, 2000 Issued
Array ( [id] => 1356838 [patent_doc_number] => 06591326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method and information processing apparatus controlling information transfer among a plurality of processors' [patent_app_type] => B1 [patent_app_number] => 09/533068 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6994 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591326.pdf [firstpage_image] =>[orig_patent_app_number] => 09533068 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533068
Method and information processing apparatus controlling information transfer among a plurality of processors Mar 21, 2000 Issued
Array ( [id] => 1425084 [patent_doc_number] => 06535943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Information processing device enabling floating interrupt to be pending and a method executing an interrupt condition change instruction' [patent_app_type] => B1 [patent_app_number] => 09/533034 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 6287 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535943.pdf [firstpage_image] =>[orig_patent_app_number] => 09533034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533034
Information processing device enabling floating interrupt to be pending and a method executing an interrupt condition change instruction Mar 21, 2000 Issued
Array ( [id] => 1395245 [patent_doc_number] => 06567884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Endian-controlled counter for synchronous ports with bus matching' [patent_app_type] => B1 [patent_app_number] => 09/531241 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4896 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567884.pdf [firstpage_image] =>[orig_patent_app_number] => 09531241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531241
Endian-controlled counter for synchronous ports with bus matching Mar 20, 2000 Issued
Array ( [id] => 7645919 [patent_doc_number] => 06477604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Computer multi-bay devices compatible expansion module and its processing procedure' [patent_app_type] => B1 [patent_app_number] => 09/531432 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1472 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477604.pdf [firstpage_image] =>[orig_patent_app_number] => 09531432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531432
Computer multi-bay devices compatible expansion module and its processing procedure Mar 19, 2000 Issued
Array ( [id] => 1308556 [patent_doc_number] => 06629181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Incremental bus structure for modular electronic equipment' [patent_app_type] => B1 [patent_app_number] => 09/527942 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629181.pdf [firstpage_image] =>[orig_patent_app_number] => 09527942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527942
Incremental bus structure for modular electronic equipment Mar 15, 2000 Issued
Array ( [id] => 1484927 [patent_doc_number] => 06453376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method for implementing scheduling mechanisms with selectable resource modes' [patent_app_type] => B1 [patent_app_number] => 09/521334 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5054 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453376.pdf [firstpage_image] =>[orig_patent_app_number] => 09521334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521334
Method for implementing scheduling mechanisms with selectable resource modes Mar 8, 2000 Issued
Array ( [id] => 4424079 [patent_doc_number] => 06301633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Generic serial interface with automatic reconfigurability' [patent_app_type] => 1 [patent_app_number] => 9/520411 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 4309 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301633.pdf [firstpage_image] =>[orig_patent_app_number] => 520411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/520411
Generic serial interface with automatic reconfigurability Mar 7, 2000 Issued
Array ( [id] => 4424434 [patent_doc_number] => 06266730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'High-frequency bus system' [patent_app_type] => 1 [patent_app_number] => 9/507303 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 7855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266730.pdf [firstpage_image] =>[orig_patent_app_number] => 507303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507303
High-frequency bus system Feb 17, 2000 Issued
Array ( [id] => 7630018 [patent_doc_number] => 06636921 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'SCSI repeater circuit with SCSI address translation and enable' [patent_app_type] => B1 [patent_app_number] => 09/507278 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8888 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636921.pdf [firstpage_image] =>[orig_patent_app_number] => 09507278 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507278
SCSI repeater circuit with SCSI address translation and enable Feb 17, 2000 Issued
Array ( [id] => 1431124 [patent_doc_number] => 06523081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Architecture using dedicated endpoints and protocol for creating a multi-application interface and improving bandwidth over universal serial bus' [patent_app_type] => B1 [patent_app_number] => 09/506764 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 13791 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523081.pdf [firstpage_image] =>[orig_patent_app_number] => 09506764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506764
Architecture using dedicated endpoints and protocol for creating a multi-application interface and improving bandwidth over universal serial bus Feb 17, 2000 Issued
Array ( [id] => 4391426 [patent_doc_number] => 06289407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Input/output device for connection and disconnection of active lines' [patent_app_type] => 1 [patent_app_number] => 9/499897 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8829 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289407.pdf [firstpage_image] =>[orig_patent_app_number] => 499897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499897
Input/output device for connection and disconnection of active lines Feb 7, 2000 Issued
Array ( [id] => 1429137 [patent_doc_number] => 06529985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Selective interception of system calls' [patent_app_type] => B1 [patent_app_number] => 09/499098 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7089 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529985.pdf [firstpage_image] =>[orig_patent_app_number] => 09499098 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499098
Selective interception of system calls Feb 3, 2000 Issued
Array ( [id] => 1533074 [patent_doc_number] => 06480916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Information processing method and system for composite appliance' [patent_app_type] => B1 [patent_app_number] => 09/491976 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 118 [patent_figures_cnt] => 128 [patent_no_of_words] => 43916 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480916.pdf [firstpage_image] =>[orig_patent_app_number] => 09491976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491976
Information processing method and system for composite appliance Jan 26, 2000 Issued
Array ( [id] => 1580256 [patent_doc_number] => 06470407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method for arbitrating interrupt priorities among peripherals in a microprocessor-based system' [patent_app_type] => B1 [patent_app_number] => 09/490961 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3128 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470407.pdf [firstpage_image] =>[orig_patent_app_number] => 09490961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/490961
Method for arbitrating interrupt priorities among peripherals in a microprocessor-based system Jan 23, 2000 Issued
Array ( [id] => 1418522 [patent_doc_number] => 06546445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and system for connecting dual storage interfaces' [patent_app_type] => B1 [patent_app_number] => 09/482231 [patent_app_country] => US [patent_app_date] => 2000-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3043 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546445.pdf [firstpage_image] =>[orig_patent_app_number] => 09482231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/482231
Method and system for connecting dual storage interfaces Jan 12, 2000 Issued
Array ( [id] => 1431356 [patent_doc_number] => 06519663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Simple enclosure services (SES) using a high-speed, point-to-point, serial bus' [patent_app_type] => B1 [patent_app_number] => 09/481537 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4637 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519663.pdf [firstpage_image] =>[orig_patent_app_number] => 09481537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481537
Simple enclosure services (SES) using a high-speed, point-to-point, serial bus Jan 11, 2000 Issued
Array ( [id] => 7644149 [patent_doc_number] => 06473825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Apparatus and method for controlling secure communications between peripheral components on computer buses connected by a bridge circuit' [patent_app_type] => B1 [patent_app_number] => 09/481331 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4923 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473825.pdf [firstpage_image] =>[orig_patent_app_number] => 09481331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481331
Apparatus and method for controlling secure communications between peripheral components on computer buses connected by a bridge circuit Jan 11, 2000 Issued
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