Rupal Dharia

Array ( [id] => 7642400 [patent_doc_number] => 06430646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and apparatus for interfacing a processor with a bus' [patent_app_type] => B1 [patent_app_number] => 09/377004 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3507 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430646.pdf [firstpage_image] =>[orig_patent_app_number] => 09377004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1505930 [patent_doc_number] => 06487621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle' [patent_app_type] => B1 [patent_app_number] => 09/375454 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5522 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487621.pdf [firstpage_image] =>[orig_patent_app_number] => 09375454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1505937 [patent_doc_number] => 06487624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method and apparatus for hot swapping and bus extension without data corruption' [patent_app_type] => B1 [patent_app_number] => 09/374051 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4673 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487624.pdf [firstpage_image] =>[orig_patent_app_number] => 09374051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1508945 [patent_doc_number] => 06467001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'VLSI chip macro interface' [patent_app_type] => B1 [patent_app_number] => 09/374222 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3920 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467001.pdf [firstpage_image] =>[orig_patent_app_number] => 09374222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1456691 [patent_doc_number] => 06457088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for programming an amplifier' [patent_app_type] => B1 [patent_app_number] => 09/357486 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9398 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457088.pdf [firstpage_image] =>[orig_patent_app_number] => 09357486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1567377 [patent_doc_number] => 06363451 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Data bus line control circuit' [patent_app_type] => B1 [patent_app_number] => 09/329263 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2327 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363451.pdf [firstpage_image] =>[orig_patent_app_number] => 09329263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495209 [patent_doc_number] => 06418491 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Apparatus and method for controlling timing of transfer requests within a data processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/339954 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6335 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418491.pdf [firstpage_image] =>[orig_patent_app_number] => 09339954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1592268 [patent_doc_number] => 06360290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Commercial standard digital bus interface circuit' [patent_app_type] => B1 [patent_app_number] => 09/338722 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4371 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360290.pdf [firstpage_image] =>[orig_patent_app_number] => 09338722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549518 [patent_doc_number] => 06374319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Flag-controlled arbitration of requesting agents' [patent_app_type] => B1 [patent_app_number] => 09/338050 [patent_app_country] => US [patent_app_date] => 1999-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 6758 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374319.pdf [firstpage_image] =>[orig_patent_app_number] => 09338050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4402708 [patent_doc_number] => 06279115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Circuit arrangement for monitoring of an electric tripping device for low-voltage switches' [patent_app_type] => 1 [patent_app_number] => 9/254198 [patent_app_country] => US [patent_app_date] => 1999-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1067 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279115.pdf [firstpage_image] =>[orig_patent_app_number] => 254198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4335009 [patent_doc_number] => 06243783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Application programming interface for managing and automating data transfer operations between applications over a bus structure' [patent_app_type] => 1 [patent_app_number] => 9/337057 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14445 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243783.pdf [firstpage_image] =>[orig_patent_app_number] => 337057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1501500 [patent_doc_number] => 06405275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'IEEE1394 common isochronous packet (CIP) enhancements for host controllers' [patent_app_type] => B1 [patent_app_number] => 09/333788 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2817 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405275.pdf [firstpage_image] =>[orig_patent_app_number] => 09333788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1326703 [patent_doc_number] => 06609169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Solid-state audio-video playback system' [patent_app_type] => B1 [patent_app_number] => 09/332541 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 13568 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609169.pdf [firstpage_image] =>[orig_patent_app_number] => 09332541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1567355 [patent_doc_number] => 06363446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method for selectively encoding bus grant lines to reduce I/O pin requirements' [patent_app_type] => B1 [patent_app_number] => 09/332278 [patent_app_country] => US [patent_app_date] => 1999-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363446.pdf [firstpage_image] =>[orig_patent_app_number] => 09332278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1567360 [patent_doc_number] => 06363447 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Apparatus for selectively encoding bus grant lines to reduce I/O pin requirements' [patent_app_type] => B1 [patent_app_number] => 09/332279 [patent_app_country] => US [patent_app_date] => 1999-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363447.pdf [firstpage_image] =>[orig_patent_app_number] => 09332279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1519620 [patent_doc_number] => 06421751 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Detecting a no-tags-free condition in a computer system having multiple outstanding transactions' [patent_app_type] => B1 [patent_app_number] => 09/330637 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 44 [patent_no_of_words] => 25204 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421751.pdf [firstpage_image] =>[orig_patent_app_number] => 09330637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1584667 [patent_doc_number] => 06449671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method and apparatus for busing data elements' [patent_app_type] => B1 [patent_app_number] => 09/328971 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4503 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449671.pdf [firstpage_image] =>[orig_patent_app_number] => 09328971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7642401 [patent_doc_number] => 06430645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Fibre channel and SCSI address mapping for multiple initiator support' [patent_app_type] => B1 [patent_app_number] => 09/328970 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4006 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430645.pdf [firstpage_image] =>[orig_patent_app_number] => 09328970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1480966 [patent_doc_number] => 06389499 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Integrated computer module' [patent_app_type] => B1 [patent_app_number] => 09/328878 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 10926 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389499.pdf [firstpage_image] =>[orig_patent_app_number] => 09328878 [rel_patent_id] =>[rel_patent_doc_number] =>)