Search

Rupal Dharia

Supervisory Patent Examiner (ID: 14113, Phone: (571)272-3880 , Office: P/2400 )

Most Active Art Unit
2181
Art Unit(s)
2400, 2492, 2189, 2443, 2781, 2181, 2305, 2456, 2100, 2441, 2141
Total Applications
417
Issued Applications
349
Pending Applications
30
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1557465 [patent_doc_number] => 06401153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-04 [patent_title] => 'Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals' [patent_app_type] => B2 [patent_app_number] => 09/329001 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4503 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401153.pdf [firstpage_image] =>[orig_patent_app_number] => 09329001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329001
Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals Jun 7, 1999 Issued
Array ( [id] => 1587300 [patent_doc_number] => 06425029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Apparatus for configuring bus architecture through software control' [patent_app_type] => B1 [patent_app_number] => 09/327413 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2623 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425029.pdf [firstpage_image] =>[orig_patent_app_number] => 09327413 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327413
Apparatus for configuring bus architecture through software control Jun 6, 1999 Issued
Array ( [id] => 1557456 [patent_doc_number] => 06401151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method for configuring bus architecture through software control' [patent_app_type] => B1 [patent_app_number] => 09/327412 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2536 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401151.pdf [firstpage_image] =>[orig_patent_app_number] => 09327412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327412
Method for configuring bus architecture through software control Jun 6, 1999 Issued
90/005381 AIRCRAFT DISPLAY AND CONTROL SYSTEM WITH VIRTUAL BACKPLANE ARCHITECTURE Jun 2, 1999 Issued
Array ( [id] => 1587288 [patent_doc_number] => 06425025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'System and method for connecting electronic circuitry in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/325688 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425025.pdf [firstpage_image] =>[orig_patent_app_number] => 09325688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325688
System and method for connecting electronic circuitry in a computer system Jun 2, 1999 Issued
Array ( [id] => 1438651 [patent_doc_number] => 06356970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Interrupt request control module with a DSP interrupt vector generator' [patent_app_type] => B1 [patent_app_number] => 09/322955 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2843 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356970.pdf [firstpage_image] =>[orig_patent_app_number] => 09322955 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322955
Interrupt request control module with a DSP interrupt vector generator May 27, 1999 Issued
Array ( [id] => 1521664 [patent_doc_number] => 06502151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Data-processing arrangement including an interrupt generator' [patent_app_type] => B2 [patent_app_number] => 09/320809 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5421 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502151.pdf [firstpage_image] =>[orig_patent_app_number] => 09320809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320809
Data-processing arrangement including an interrupt generator May 26, 1999 Issued
Array ( [id] => 1519722 [patent_doc_number] => 06421783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Microprocessor and main board mounting arrangement' [patent_app_type] => B1 [patent_app_number] => 09/321109 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 675 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421783.pdf [firstpage_image] =>[orig_patent_app_number] => 09321109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321109
Microprocessor and main board mounting arrangement May 26, 1999 Issued
Array ( [id] => 1526543 [patent_doc_number] => 06353893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Sleep mode indicator for a battery-operated device' [patent_app_type] => B1 [patent_app_number] => 09/317742 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3168 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353893.pdf [firstpage_image] =>[orig_patent_app_number] => 09317742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317742
Sleep mode indicator for a battery-operated device May 23, 1999 Issued
Array ( [id] => 1568627 [patent_doc_number] => 06339807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Multiprocessor system and the bus arbitrating method of the same' [patent_app_type] => B1 [patent_app_number] => 09/310942 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5494 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339807.pdf [firstpage_image] =>[orig_patent_app_number] => 09310942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310942
Multiprocessor system and the bus arbitrating method of the same May 12, 1999 Issued
Array ( [id] => 1466735 [patent_doc_number] => 06351820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'PC card with automated drag and sleep function' [patent_app_type] => B1 [patent_app_number] => 09/298614 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3636 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351820.pdf [firstpage_image] =>[orig_patent_app_number] => 09298614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298614
PC card with automated drag and sleep function Apr 25, 1999 Issued
Array ( [id] => 4292033 [patent_doc_number] => 06247085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and apparatus for removable peripheral user interface panels' [patent_app_type] => 1 [patent_app_number] => 9/285875 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1128 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247085.pdf [firstpage_image] =>[orig_patent_app_number] => 285875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285875
Method and apparatus for removable peripheral user interface panels Mar 30, 1999 Issued
Array ( [id] => 1505948 [patent_doc_number] => 06487628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Peripheral component interface with multiple data channels and reduced latency over a system area network' [patent_app_type] => B1 [patent_app_number] => 09/283773 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8167 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487628.pdf [firstpage_image] =>[orig_patent_app_number] => 09283773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283773
Peripheral component interface with multiple data channels and reduced latency over a system area network Mar 30, 1999 Issued
Array ( [id] => 1572284 [patent_doc_number] => 06378027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'System upgrade and processor service' [patent_app_type] => B1 [patent_app_number] => 09/281080 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378027.pdf [firstpage_image] =>[orig_patent_app_number] => 09281080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281080
System upgrade and processor service Mar 29, 1999 Issued
Array ( [id] => 1495269 [patent_doc_number] => 06418501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Memory card' [patent_app_type] => B1 [patent_app_number] => 09/280708 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5261 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418501.pdf [firstpage_image] =>[orig_patent_app_number] => 09280708 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280708
Memory card Mar 29, 1999 Issued
Array ( [id] => 4324437 [patent_doc_number] => 06327635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Add-on card with automatic bus power line selection circuit' [patent_app_type] => 1 [patent_app_number] => 9/281369 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3393 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327635.pdf [firstpage_image] =>[orig_patent_app_number] => 281369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281369
Add-on card with automatic bus power line selection circuit Mar 29, 1999 Issued
Array ( [id] => 1459971 [patent_doc_number] => 06463495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Command and control infrastructure for a computer system using the computer\'s power rail' [patent_app_type] => B1 [patent_app_number] => 09/280311 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4694 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463495.pdf [firstpage_image] =>[orig_patent_app_number] => 09280311 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280311
Command and control infrastructure for a computer system using the computer's power rail Mar 28, 1999 Issued
Array ( [id] => 1604468 [patent_doc_number] => 06434654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'System bus with a variable width selectivity configurable at initialization' [patent_app_type] => B1 [patent_app_number] => 09/277569 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434654.pdf [firstpage_image] =>[orig_patent_app_number] => 09277569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277569
System bus with a variable width selectivity configurable at initialization Mar 25, 1999 Issued
Array ( [id] => 4387893 [patent_doc_number] => 06275884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method for interconnecting components within a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/276383 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2598 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275884.pdf [firstpage_image] =>[orig_patent_app_number] => 276383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276383
Method for interconnecting components within a data processing system Mar 24, 1999 Issued
Array ( [id] => 1568622 [patent_doc_number] => 06339806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Primary bus to secondary bus multiplexing for I2C and other serial buses' [patent_app_type] => B1 [patent_app_number] => 09/273663 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2759 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339806.pdf [firstpage_image] =>[orig_patent_app_number] => 09273663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273663
Primary bus to secondary bus multiplexing for I2C and other serial buses Mar 22, 1999 Issued
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