Search

Rupal Dharia

Supervisory Patent Examiner (ID: 2589, Phone: (571)272-3880 , Office: P/2400 )

Most Active Art Unit
2181
Art Unit(s)
2181, 2781, 2492, 2305, 2400, 2100, 2456, 2141, 2189, 2443, 2441
Total Applications
412
Issued Applications
349
Pending Applications
25
Abandoned Applications
39

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1438651 [patent_doc_number] => 06356970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Interrupt request control module with a DSP interrupt vector generator' [patent_app_type] => B1 [patent_app_number] => 09/322955 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2843 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356970.pdf [firstpage_image] =>[orig_patent_app_number] => 09322955 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322955
Interrupt request control module with a DSP interrupt vector generator May 27, 1999 Issued
Array ( [id] => 1519722 [patent_doc_number] => 06421783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Microprocessor and main board mounting arrangement' [patent_app_type] => B1 [patent_app_number] => 09/321109 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 675 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421783.pdf [firstpage_image] =>[orig_patent_app_number] => 09321109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321109
Microprocessor and main board mounting arrangement May 26, 1999 Issued
Array ( [id] => 1521664 [patent_doc_number] => 06502151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Data-processing arrangement including an interrupt generator' [patent_app_type] => B2 [patent_app_number] => 09/320809 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5421 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502151.pdf [firstpage_image] =>[orig_patent_app_number] => 09320809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320809
Data-processing arrangement including an interrupt generator May 26, 1999 Issued
Array ( [id] => 1526543 [patent_doc_number] => 06353893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Sleep mode indicator for a battery-operated device' [patent_app_type] => B1 [patent_app_number] => 09/317742 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3168 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353893.pdf [firstpage_image] =>[orig_patent_app_number] => 09317742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317742
Sleep mode indicator for a battery-operated device May 23, 1999 Issued
Array ( [id] => 1568627 [patent_doc_number] => 06339807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Multiprocessor system and the bus arbitrating method of the same' [patent_app_type] => B1 [patent_app_number] => 09/310942 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5494 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339807.pdf [firstpage_image] =>[orig_patent_app_number] => 09310942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310942
Multiprocessor system and the bus arbitrating method of the same May 12, 1999 Issued
Array ( [id] => 1466735 [patent_doc_number] => 06351820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'PC card with automated drag and sleep function' [patent_app_type] => B1 [patent_app_number] => 09/298614 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3636 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351820.pdf [firstpage_image] =>[orig_patent_app_number] => 09298614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298614
PC card with automated drag and sleep function Apr 25, 1999 Issued
Array ( [id] => 4292033 [patent_doc_number] => 06247085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and apparatus for removable peripheral user interface panels' [patent_app_type] => 1 [patent_app_number] => 9/285875 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1128 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247085.pdf [firstpage_image] =>[orig_patent_app_number] => 285875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/285875
Method and apparatus for removable peripheral user interface panels Mar 30, 1999 Issued
Array ( [id] => 1505948 [patent_doc_number] => 06487628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Peripheral component interface with multiple data channels and reduced latency over a system area network' [patent_app_type] => B1 [patent_app_number] => 09/283773 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8167 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487628.pdf [firstpage_image] =>[orig_patent_app_number] => 09283773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283773
Peripheral component interface with multiple data channels and reduced latency over a system area network Mar 30, 1999 Issued
Array ( [id] => 1572284 [patent_doc_number] => 06378027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'System upgrade and processor service' [patent_app_type] => B1 [patent_app_number] => 09/281080 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378027.pdf [firstpage_image] =>[orig_patent_app_number] => 09281080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281080
System upgrade and processor service Mar 29, 1999 Issued
Array ( [id] => 4324437 [patent_doc_number] => 06327635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Add-on card with automatic bus power line selection circuit' [patent_app_type] => 1 [patent_app_number] => 9/281369 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3393 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327635.pdf [firstpage_image] =>[orig_patent_app_number] => 281369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281369
Add-on card with automatic bus power line selection circuit Mar 29, 1999 Issued
Array ( [id] => 1495269 [patent_doc_number] => 06418501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Memory card' [patent_app_type] => B1 [patent_app_number] => 09/280708 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5261 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418501.pdf [firstpage_image] =>[orig_patent_app_number] => 09280708 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280708
Memory card Mar 29, 1999 Issued
Array ( [id] => 1459971 [patent_doc_number] => 06463495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Command and control infrastructure for a computer system using the computer\'s power rail' [patent_app_type] => B1 [patent_app_number] => 09/280311 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4694 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463495.pdf [firstpage_image] =>[orig_patent_app_number] => 09280311 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280311
Command and control infrastructure for a computer system using the computer's power rail Mar 28, 1999 Issued
Array ( [id] => 1604468 [patent_doc_number] => 06434654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'System bus with a variable width selectivity configurable at initialization' [patent_app_type] => B1 [patent_app_number] => 09/277569 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434654.pdf [firstpage_image] =>[orig_patent_app_number] => 09277569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277569
System bus with a variable width selectivity configurable at initialization Mar 25, 1999 Issued
Array ( [id] => 4387893 [patent_doc_number] => 06275884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method for interconnecting components within a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/276383 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2598 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275884.pdf [firstpage_image] =>[orig_patent_app_number] => 276383 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276383
Method for interconnecting components within a data processing system Mar 24, 1999 Issued
Array ( [id] => 1568622 [patent_doc_number] => 06339806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Primary bus to secondary bus multiplexing for I2C and other serial buses' [patent_app_type] => B1 [patent_app_number] => 09/273663 [patent_app_country] => US [patent_app_date] => 1999-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2759 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339806.pdf [firstpage_image] =>[orig_patent_app_number] => 09273663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273663
Primary bus to secondary bus multiplexing for I2C and other serial buses Mar 22, 1999 Issued
Array ( [id] => 1526411 [patent_doc_number] => 06353865 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Terminator with indicator' [patent_app_type] => B1 [patent_app_number] => 09/273454 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2664 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353865.pdf [firstpage_image] =>[orig_patent_app_number] => 09273454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273454
Terminator with indicator Mar 21, 1999 Issued
Array ( [id] => 4366003 [patent_doc_number] => 06286069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Device which uses NOP command to share memory bus' [patent_app_type] => 1 [patent_app_number] => 9/270029 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1700 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286069.pdf [firstpage_image] =>[orig_patent_app_number] => 270029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270029
Device which uses NOP command to share memory bus Mar 15, 1999 Issued
Array ( [id] => 4388922 [patent_doc_number] => 06275949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Power controller for a peripheral device that stores the on/off state thereof when power is removed from the device' [patent_app_type] => 1 [patent_app_number] => 9/267677 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3594 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275949.pdf [firstpage_image] =>[orig_patent_app_number] => 267677 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/267677
Power controller for a peripheral device that stores the on/off state thereof when power is removed from the device Mar 14, 1999 Issued
Array ( [id] => 4349364 [patent_doc_number] => 06321284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Multiprocessor system with multiple memory buses for access to shared memories' [patent_app_type] => 1 [patent_app_number] => 9/268426 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6516 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321284.pdf [firstpage_image] =>[orig_patent_app_number] => 268426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268426
Multiprocessor system with multiple memory buses for access to shared memories Mar 11, 1999 Issued
Array ( [id] => 4366018 [patent_doc_number] => 06286070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Shared memory access device and method' [patent_app_type] => 1 [patent_app_number] => 9/257040 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5118 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286070.pdf [firstpage_image] =>[orig_patent_app_number] => 257040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257040
Shared memory access device and method Feb 24, 1999 Issued
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