Search

Russell G. Fiebig

Examiner (ID: 14740, Phone: (571)270-5366 , Office: P/1655 )

Most Active Art Unit
1655
Art Unit(s)
1655
Total Applications
1057
Issued Applications
630
Pending Applications
106
Abandoned Applications
368

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14692887 [patent_doc_number] => 20190245559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/390393 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390393 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390393
Transmitter and parity permutation method thereof Apr 21, 2019 Issued
Array ( [id] => 15622741 [patent_doc_number] => 20200081775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => CONTROLLER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/381210 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381210
Controller and method of operating the same Apr 10, 2019 Issued
Array ( [id] => 16378015 [patent_doc_number] => 20200326857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => MANAGING PARITY INFORMATION FOR DATA STORED ON A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/381969 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381969 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381969
Managing parity information for data stored on a storage device Apr 10, 2019 Issued
Array ( [id] => 15155869 [patent_doc_number] => 20190356412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => FAST TERMINATION OF MULTILANE DOUBLE DATA RATE TRANSACTIONS [patent_app_type] => utility [patent_app_number] => 16/381415 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381415
FAST TERMINATION OF MULTILANE DOUBLE DATA RATE TRANSACTIONS Apr 10, 2019 Abandoned
Array ( [id] => 19427954 [patent_doc_number] => 12087382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Adaptive threshold for bad flash memory blocks [patent_app_type] => utility [patent_app_number] => 16/381581 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 35464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381581
Adaptive threshold for bad flash memory blocks Apr 10, 2019 Issued
Array ( [id] => 16758570 [patent_doc_number] => 10977119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Techniques for utilizing volatile memory buffers to reduce parity information stored on a storage device [patent_app_type] => utility [patent_app_number] => 16/382046 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382046
Techniques for utilizing volatile memory buffers to reduce parity information stored on a storage device Apr 10, 2019 Issued
Array ( [id] => 14627509 [patent_doc_number] => 20190227122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => RE-PROGRAMMABLE SELF-TEST [patent_app_type] => utility [patent_app_number] => 16/371316 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371316 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371316
Re-programmable self-test Mar 31, 2019 Issued
Array ( [id] => 14632763 [patent_doc_number] => 20190229754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 16/369742 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369742 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369742
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 1024-symbol mapping, and bit interleaving method using same Mar 28, 2019 Issued
Array ( [id] => 14589249 [patent_doc_number] => 20190222233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 16/365533 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16365533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/365533
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 4096-symbol mapping, and bit interleaving method using same Mar 25, 2019 Issued
Array ( [id] => 16395317 [patent_doc_number] => 20200336258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => MULTI-ACCESS MANAGEMENT SERVICES PACKET RECOVERY MECHANISMS [patent_app_type] => utility [patent_app_number] => 16/956358 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16956358 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/956358
Multi-access management services packet recovery mechanisms Mar 25, 2019 Issued
Array ( [id] => 16654204 [patent_doc_number] => 10931402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Distributed storage system data management and security [patent_app_type] => utility [patent_app_number] => 16/362209 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362209
Distributed storage system data management and security Mar 21, 2019 Issued
Array ( [id] => 16330802 [patent_doc_number] => 20200301768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => MANAGING THE RELIABILITY OF PAGES IN NON-VOLATILE RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 16/357049 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357049 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/357049
Managing the reliability of pages in non-volatile random access memory Mar 17, 2019 Issued
Array ( [id] => 17940443 [patent_doc_number] => 11474897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Techniques for storing data to enhance recovery and detection of data corruption errors [patent_app_type] => utility [patent_app_number] => 16/355309 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5486 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/355309
Techniques for storing data to enhance recovery and detection of data corruption errors Mar 14, 2019 Issued
Array ( [id] => 17078640 [patent_doc_number] => 11115062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Memory system with adaptive threshold decoding and method of operating such memory system [patent_app_type] => utility [patent_app_number] => 16/355247 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355247 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/355247
Memory system with adaptive threshold decoding and method of operating such memory system Mar 14, 2019 Issued
Array ( [id] => 16974249 [patent_doc_number] => 11070234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Memory system with hybrid decoding scheme with information exchange and method of operating such memory system [patent_app_type] => utility [patent_app_number] => 16/355325 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6256 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355325 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/355325
Memory system with hybrid decoding scheme with information exchange and method of operating such memory system Mar 14, 2019 Issued
Array ( [id] => 17379886 [patent_doc_number] => 11237902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Systems and methods for an ECC architecture with memory mapping [patent_app_type] => utility [patent_app_number] => 16/354231 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6728 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16354231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/354231
Systems and methods for an ECC architecture with memory mapping Mar 14, 2019 Issued
Array ( [id] => 14475179 [patent_doc_number] => 20190189236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => ARTIFICIAL INTELLIGENCE BASED MONITORING OF SOLID STATE DRIVES AND DUAL IN-LINE MEMORY MODULES [patent_app_type] => utility [patent_app_number] => 16/281559 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281559
Artificial intelligence based monitoring of solid state drives and dual in-line memory modules Feb 20, 2019 Issued
Array ( [id] => 16669158 [patent_doc_number] => 10938420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => System and methods for low complexity list decoding of turbo codes and convolutional codes [patent_app_type] => utility [patent_app_number] => 16/272722 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8253 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272722
System and methods for low complexity list decoding of turbo codes and convolutional codes Feb 10, 2019 Issued
Array ( [id] => 16911923 [patent_doc_number] => 11043976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => System and methods for low complexity list decoding of turbo codes and convolutional codes [patent_app_type] => utility [patent_app_number] => 16/272653 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8632 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272653
System and methods for low complexity list decoding of turbo codes and convolutional codes Feb 10, 2019 Issued
Array ( [id] => 17254701 [patent_doc_number] => 11190209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Expansion for Blaum-Roth codes [patent_app_type] => utility [patent_app_number] => 16/262599 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 8920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262599 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262599
Expansion for Blaum-Roth codes Jan 29, 2019 Issued
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