Russell G. Fiebig

Array ( [id] => 14138985 [patent_doc_number] => 20190103882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => LOW BER HARD-DECISION LDPC DECODER [patent_app_type] => utility [patent_app_number] => 16/137947 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14870909 [patent_doc_number] => 20190285696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SEMICONDUCTOR DEVICE AND FAILURE DIAGNOSIS METHOD [patent_app_type] => utility [patent_app_number] => 16/127650 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14811213 [patent_doc_number] => 20190272216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => DATA STORAGE DEVICE AND METHOD OF OPERATING [patent_app_type] => utility [patent_app_number] => 16/124227 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16759615 [patent_doc_number] => 10978170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Method and system for monitoring information of a memory module in real time [patent_app_type] => utility [patent_app_number] => 16/124379 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9301 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14903825 [patent_doc_number] => 20190295678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/124961 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16957887 [patent_doc_number] => 11061750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Corrupted track analyzer [patent_app_type] => utility [patent_app_number] => 16/124153 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4648 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18372380 [patent_doc_number] => 11652566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Forward error correction with outer multi-level code and inner contrast code [patent_app_type] => utility [patent_app_number] => 16/603623 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 13234 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15141283 [patent_doc_number] => 10484140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Packet retransmission and memory sharing [patent_app_type] => utility [patent_app_number] => 16/046494 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 12304 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17031503 [patent_doc_number] => 11093314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Time-sequential data diagnosis device, additional learning method, and recording medium [patent_app_type] => utility [patent_app_number] => 15/734229 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6515 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15734229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15366055 [patent_doc_number] => 20200018792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => Electronic Interface for Configuring Electronic Communications in Electronic Testing [patent_app_type] => utility [patent_app_number] => 16/034263 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16034263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16478221 [patent_doc_number] => 10853169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory controller, semiconductor memory system including the same, and method of driving the semiconductor memory system [patent_app_type] => utility [patent_app_number] => 16/029083 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7668 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17247961 [patent_doc_number] => 20210367706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => DEVICE COMMUNICATION INTERPRETATION BASED ON PROCESS STATE [patent_app_type] => utility [patent_app_number] => 16/606357 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16606357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17970077 [patent_doc_number] => 11487610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Methods for parity error alert timing interlock and memory devices and systems employing the same [patent_app_type] => utility [patent_app_number] => 15/975703 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17682464 [patent_doc_number] => 11366717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Systems and methods for error correction [patent_app_type] => utility [patent_app_number] => 16/605620 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8348 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14997789 [patent_doc_number] => 20190317852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => Efficient Content-Addressable Memory Lookup Result Integrity Checking and Correcting Operations Including for Protecting the Accuracy of Packet Processing Operations [patent_app_type] => utility [patent_app_number] => 15/954488 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16416610 [patent_doc_number] => 10824504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Common high and low random bit error correction logic [patent_app_type] => utility [patent_app_number] => 15/953805 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15953805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13347269 [patent_doc_number] => 20180225174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => STORAGE CLUSTER [patent_app_type] => utility [patent_app_number] => 15/941580 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16431150 [patent_doc_number] => 10831231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Circuit for and method of implementing a polar decoder [patent_app_type] => utility [patent_app_number] => 15/939255 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7221 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14574813 [patent_doc_number] => 20190215014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => ENCODING AND DECODING OF HAMMING DISTANCE-BASED BINARY REPRESENTATIONS OF NUMBERS [patent_app_type] => utility [patent_app_number] => 15/933697 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13453453 [patent_doc_number] => 20180278269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => METHOD AND APPARATUS FOR RATE-MATCHING OF POLAR CODES [patent_app_type] => utility [patent_app_number] => 15/934878 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934878 [rel_patent_id] =>[rel_patent_doc_number] =>)