Search

Russell G. Fiebig

Examiner (ID: 14740, Phone: (571)270-5366 , Office: P/1655 )

Most Active Art Unit
1655
Art Unit(s)
1655
Total Applications
1057
Issued Applications
630
Pending Applications
106
Abandoned Applications
368

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17211368 [patent_doc_number] => 11171758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Code block grouping and feedback that support efficient retransmissions [patent_app_type] => utility [patent_app_number] => 15/933110 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 19942 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933110 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933110
Code block grouping and feedback that support efficient retransmissions Mar 21, 2018 Issued
Array ( [id] => 15761775 [patent_doc_number] => 10623025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Operating method of memory system [patent_app_type] => utility [patent_app_number] => 15/914638 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 22358 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914638
Operating method of memory system Mar 6, 2018 Issued
Array ( [id] => 17320118 [patent_doc_number] => 20210409168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => ELECTRONIC APPARATUS AND METHOD FOR WIRELESS COMMUNICATION NETWORK CONTROL END AND NETWORK NODE [patent_app_type] => utility [patent_app_number] => 16/491160 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16491160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/491160
Electronic apparatus and method for wireless communication network control end and network node Mar 4, 2018 Issued
Array ( [id] => 15704949 [patent_doc_number] => 10608669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Performance of data channel using polar codes for a wireless communication system [patent_app_type] => utility [patent_app_number] => 15/932232 [patent_app_country] => US [patent_app_date] => 2018-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15932232 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/932232
Performance of data channel using polar codes for a wireless communication system Feb 15, 2018 Issued
Array ( [id] => 16171544 [patent_doc_number] => 10713114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Memory module and operation method of the same [patent_app_type] => utility [patent_app_number] => 15/897265 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6354 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15897265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/897265
Memory module and operation method of the same Feb 14, 2018 Issued
Array ( [id] => 12781291 [patent_doc_number] => 20180152266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => COMMUNICATION METHOD AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 15/879709 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879709 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879709
Communication method and communication device Jan 24, 2018 Issued
Array ( [id] => 14632759 [patent_doc_number] => 20190229752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => APPARATUS AND METHODS FOR POLAR CODE CONSTRUCTION AND BIT POSITION ALLOCATION [patent_app_type] => utility [patent_app_number] => 15/875403 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875403
Apparatus and methods for polar code construction and bit position allocation Jan 18, 2018 Issued
Array ( [id] => 12741277 [patent_doc_number] => 20180138926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => RS ERROR CORRECTION DECODING METHOD [patent_app_type] => utility [patent_app_number] => 15/871939 [patent_app_country] => US [patent_app_date] => 2018-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/871939
RS error correction decoding method Jan 14, 2018 Issued
Array ( [id] => 14234585 [patent_doc_number] => 20190129465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SKEW CORRECTION FOR SOURCE SYNCHRONOUS SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/858460 [patent_app_country] => US [patent_app_date] => 2017-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15858460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/858460
Skew correction for source synchronous systems Dec 28, 2017 Issued
Array ( [id] => 16202786 [patent_doc_number] => 10727977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => System and method for improving forward error correction efficiency [patent_app_type] => utility [patent_app_number] => 15/856650 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5022 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15856650 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/856650
System and method for improving forward error correction efficiency Dec 27, 2017 Issued
Array ( [id] => 14218619 [patent_doc_number] => 20190121694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") MEMORY DEVICE AND CORRECTING FAILURE BITS THEREFROM BY USING ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 15/855910 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855910
Over-voltage write operation of tunnel magnet-resistance ("TMR") memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques Dec 26, 2017 Issued
Array ( [id] => 14506489 [patent_doc_number] => 20190196899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => INTEGRATION ERROR DETECTION AND CORRECTION SYSTEM [patent_app_type] => utility [patent_app_number] => 15/854659 [patent_app_country] => US [patent_app_date] => 2017-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854659
Integration error detection and correction system Dec 25, 2017 Issued
Array ( [id] => 13738249 [patent_doc_number] => 20180373594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => SEMICONDUCTOR DEVICE AND ERROR MANAGEMENT METHOD [patent_app_type] => utility [patent_app_number] => 15/854191 [patent_app_country] => US [patent_app_date] => 2017-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854191
Semiconductor device and error management method Dec 25, 2017 Issued
Array ( [id] => 14504587 [patent_doc_number] => 20190195948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => SELF TESTING CIRCUIT FOR POWER OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 15/852407 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15852407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/852407
Self testing circuit for power optimization Dec 21, 2017 Issued
Array ( [id] => 12653352 [patent_doc_number] => 20180109615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => READ-PREPARE REQUESTS TO MULTIPLE MEMORIES [patent_app_type] => utility [patent_app_number] => 15/841936 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841936
Read-prepare requests to multiple memories Dec 13, 2017 Issued
Array ( [id] => 14177321 [patent_doc_number] => 10262681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Reliable data reading with data set screening by error injection [patent_app_type] => utility [patent_app_number] => 15/824909 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7461 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824909 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824909
Reliable data reading with data set screening by error injection Nov 27, 2017 Issued
Array ( [id] => 12262562 [patent_doc_number] => 20180081758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SELF-OPTIMIZING READ-AHEAD' [patent_app_type] => utility [patent_app_number] => 15/823251 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6920 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823251 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/823251
Self-optimizing read-ahead Nov 26, 2017 Issued
Array ( [id] => 14858775 [patent_doc_number] => 10418121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Memory system with diagnose command and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/812472 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3354 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812472
Memory system with diagnose command and operating method thereof Nov 13, 2017 Issued
Array ( [id] => 14078897 [patent_doc_number] => 20190088336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => DECODING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/811695 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811695 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811695
Decoding method, memory controlling circuit unit and memory storage device Nov 13, 2017 Issued
Array ( [id] => 15106407 [patent_doc_number] => 10474529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Error checking and correcting decoding method and apparatus [patent_app_type] => utility [patent_app_number] => 15/808808 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8116 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808808
Error checking and correcting decoding method and apparatus Nov 8, 2017 Issued
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