
Russell G. Fiebig
Examiner (ID: 14740, Phone: (571)270-5366 , Office: P/1655 )
| Most Active Art Unit | 1655 |
| Art Unit(s) | 1655 |
| Total Applications | 1057 |
| Issued Applications | 630 |
| Pending Applications | 106 |
| Abandoned Applications | 368 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19266770
[patent_doc_number] => 20240210471
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => ELECTRONIC DEVICE AND METHOD OF TESTING ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/338471
[patent_app_country] => US
[patent_app_date] => 2023-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13594
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338471
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/338471 | ELECTRONIC DEVICE AND METHOD OF TESTING ELECTRONIC DEVICE | Jun 20, 2023 | Pending |
Array
(
[id] => 19347422
[patent_doc_number] => 20240256385
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => DATA STORAGE SYSTEM AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/335606
[patent_app_country] => US
[patent_app_date] => 2023-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2423
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18335606
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/335606 | DATA STORAGE SYSTEM AND OPERATION METHOD THEREOF | Jun 14, 2023 | Pending |
Array
(
[id] => 19524616
[patent_doc_number] => 12126360
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Apparatus and method for generating low-density parity-check (LDPC) code
[patent_app_type] => utility
[patent_app_number] => 18/207233
[patent_app_country] => US
[patent_app_date] => 2023-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5166
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207233
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/207233 | Apparatus and method for generating low-density parity-check (LDPC) code | Jun 7, 2023 | Issued |
Array
(
[id] => 19634351
[patent_doc_number] => 20240412800
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => SYSTEM AND METHOD FOR TESTING MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/206772
[patent_app_country] => US
[patent_app_date] => 2023-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8957
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206772
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/206772 | System and method for testing memory device | Jun 6, 2023 | Issued |
Array
(
[id] => 19587684
[patent_doc_number] => 20240385241
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION
[patent_app_type] => utility
[patent_app_number] => 18/199065
[patent_app_country] => US
[patent_app_date] => 2023-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3953
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199065
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/199065 | CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION | May 17, 2023 | Pending |
Array
(
[id] => 19295089
[patent_doc_number] => 12034459
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Memory controller, memory system, and memory control method
[patent_app_type] => utility
[patent_app_number] => 18/312834
[patent_app_country] => US
[patent_app_date] => 2023-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 7099
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312834
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/312834 | Memory controller, memory system, and memory control method | May 4, 2023 | Issued |
Array
(
[id] => 19442435
[patent_doc_number] => 12092690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-17
[patent_title] => Emulation of JTAG/SCAN test interface protocols using SPI communication device
[patent_app_type] => utility
[patent_app_number] => 18/140930
[patent_app_country] => US
[patent_app_date] => 2023-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5500
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 294
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140930
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/140930 | Emulation of JTAG/SCAN test interface protocols using SPI communication device | Apr 27, 2023 | Issued |
Array
(
[id] => 20461002
[patent_doc_number] => 20260010430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-08
[patent_title] => BIT SPREADING TECHNIQUE FOR RADIATION HARDENED ERROR RESISTANT MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/303933
[patent_app_country] => US
[patent_app_date] => 2023-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2247
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303933
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/303933 | BIT SPREADING TECHNIQUE FOR RADIATION HARDENED ERROR RESISTANT MEMORY SYSTEM | Apr 19, 2023 | Pending |
Array
(
[id] => 18832606
[patent_doc_number] => 20230401133
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => MEMORY TEST DRIVE
[patent_app_type] => utility
[patent_app_number] => 18/301842
[patent_app_country] => US
[patent_app_date] => 2023-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6020
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301842
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/301842 | Memory test drive | Apr 16, 2023 | Issued |
Array
(
[id] => 19842536
[patent_doc_number] => 12254935
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-18
[patent_title] => Use of configurable phase range to detect DDR read and write bursts
[patent_app_type] => utility
[patent_app_number] => 18/298467
[patent_app_country] => US
[patent_app_date] => 2023-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4041
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298467
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/298467 | Use of configurable phase range to detect DDR read and write bursts | Apr 10, 2023 | Issued |
Array
(
[id] => 19405701
[patent_doc_number] => 20240289212
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => Bit Efficient Memory Error Correcting Coding And Decoding Scheme
[patent_app_type] => utility
[patent_app_number] => 18/132686
[patent_app_country] => US
[patent_app_date] => 2023-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6199
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132686
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/132686 | Bit efficient memory error correcting coding and decoding scheme | Apr 9, 2023 | Issued |
Array
(
[id] => 19597625
[patent_doc_number] => 12155482
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-26
[patent_title] => Hierarchical deep channel coding
[patent_app_type] => utility
[patent_app_number] => 18/130156
[patent_app_country] => US
[patent_app_date] => 2023-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4328
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18130156
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/130156 | Hierarchical deep channel coding | Apr 2, 2023 | Issued |
Array
(
[id] => 18676880
[patent_doc_number] => 20230314513
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => IN-CIRCUIT EMULATOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/192488
[patent_app_country] => US
[patent_app_date] => 2023-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4751
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192488
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/192488 | IN-CIRCUIT EMULATOR DEVICE | Mar 28, 2023 | Abandoned |
Array
(
[id] => 20274692
[patent_doc_number] => 12444476
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Host controlled media testing of memory
[patent_app_type] => utility
[patent_app_number] => 18/120086
[patent_app_country] => US
[patent_app_date] => 2023-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 0
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120086
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/120086 | Host controlled media testing of memory | Mar 9, 2023 | Issued |
Array
(
[id] => 19433933
[patent_doc_number] => 20240302431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => HIGH THROUGHPUT SORT
[patent_app_type] => utility
[patent_app_number] => 18/179593
[patent_app_country] => US
[patent_app_date] => 2023-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4249
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179593
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/179593 | High throughput sort | Mar 6, 2023 | Issued |
Array
(
[id] => 20123129
[patent_doc_number] => 20250238160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-24
[patent_title] => DATA PROCESSING METHOD AND APPARATUS, AND STORAGE SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/697754
[patent_app_country] => US
[patent_app_date] => 2023-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12467
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 16
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18697754
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/697754 | DATA PROCESSING METHOD AND APPARATUS, AND STORAGE SYSTEM | Mar 5, 2023 | Pending |
Array
(
[id] => 19858828
[patent_doc_number] => 12261690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Coordinated edge-assisted reliability mechanism for real-time media services
[patent_app_type] => utility
[patent_app_number] => 18/170960
[patent_app_country] => US
[patent_app_date] => 2023-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 9918
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170960
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/170960 | Coordinated edge-assisted reliability mechanism for real-time media services | Feb 16, 2023 | Issued |
Array
(
[id] => 19595252
[patent_doc_number] => 12153089
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-26
[patent_title] => Electronic device for self-testing period of clock signal and monitoring method thereof
[patent_app_type] => utility
[patent_app_number] => 18/165490
[patent_app_country] => US
[patent_app_date] => 2023-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7109
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165490
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/165490 | Electronic device for self-testing period of clock signal and monitoring method thereof | Feb 6, 2023 | Issued |
Array
(
[id] => 18541635
[patent_doc_number] => 20230246751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => Full Adaptive Target BLER LTE Feature
[patent_app_type] => utility
[patent_app_number] => 18/161887
[patent_app_country] => US
[patent_app_date] => 2023-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6851
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161887
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/161887 | Full Adaptive Target BLER LTE Feature | Jan 29, 2023 | Abandoned |
Array
(
[id] => 18569086
[patent_doc_number] => 20230259422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-17
[patent_title] => MEMORY SYSTEM INCLUDING DATA-WIDTH AWARE ENCODER AND DATA-WIDTH AWARE DECODER AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/102187
[patent_app_country] => US
[patent_app_date] => 2023-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12737
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18102187
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/102187 | Memory system including data-width aware encoder and data-width aware decoder and operating method thereof | Jan 26, 2023 | Issued |