Search

Russell G. Fiebig

Examiner (ID: 14740, Phone: (571)270-5366 , Office: P/1655 )

Most Active Art Unit
1655
Art Unit(s)
1655
Total Applications
1057
Issued Applications
630
Pending Applications
106
Abandoned Applications
368

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18646130 [patent_doc_number] => 11770215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Transceiver system with end-to-end reliability and ordering protocols [patent_app_type] => utility [patent_app_number] => 17/674167 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 47 [patent_no_of_words] => 22431 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674167
Transceiver system with end-to-end reliability and ordering protocols Feb 16, 2022 Issued
Array ( [id] => 17737760 [patent_doc_number] => 20220223222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => POST PACKAGE REPAIRING METHOD AND APPARATUS FOR MEMORY, STORAGE MEDIUM, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/669538 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669538
POST PACKAGE REPAIRING METHOD AND APPARATUS FOR MEMORY, STORAGE MEDIUM, AND ELECTRONIC DEVICE Feb 10, 2022 Abandoned
Array ( [id] => 17631539 [patent_doc_number] => 20220166554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => PACKET RETRANSMISSION AND MEMORY SHARING [patent_app_type] => utility [patent_app_number] => 17/666728 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666728
PACKET RETRANSMISSION AND MEMORY SHARING Feb 7, 2022 Abandoned
Array ( [id] => 18541624 [patent_doc_number] => 20230246740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => Systems and Methods for Providing End-to-End Data Protection [patent_app_type] => utility [patent_app_number] => 17/588832 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588832
Systems and methods for providing end-to-end data protection Jan 30, 2022 Issued
Array ( [id] => 18531841 [patent_doc_number] => 20230236913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => STORAGE ERROR IDENTIFICATION/REDUCTION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/583272 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583272
Storage error identification/reduction system Jan 24, 2022 Issued
Array ( [id] => 19079277 [patent_doc_number] => 11948652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Formal verification tool to verify hardware design of memory unit [patent_app_type] => utility [patent_app_number] => 17/573542 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573542
Formal verification tool to verify hardware design of memory unit Jan 10, 2022 Issued
Array ( [id] => 18489254 [patent_doc_number] => 20230216605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SELF-DECODABLE DATA PORTION FOR PHYSICAL UPLINK REPETITION [patent_app_type] => utility [patent_app_number] => 17/647254 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647254
Self-decodable data portion for physical uplink repetition Jan 5, 2022 Issued
Array ( [id] => 17693435 [patent_doc_number] => 20220200728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => BROADCAST SIGNAL TRANSMISSION DEVICE, BROADCAST SIGNAL RECEPTION DEVICE, BROADCAST SIGNAL TRANSMISSION METHOD, AND BROADCAST SIGNAL RECEPTION METHOD [patent_app_type] => utility [patent_app_number] => 17/565965 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565965
Broadcast signal transmission device, broadcast signal reception device, broadcast signal transmission method, and broadcast signal reception method Dec 29, 2021 Issued
Array ( [id] => 18949634 [patent_doc_number] => 11892927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Method for error handling of an interconnection protocol, controller and storage device [patent_app_type] => utility [patent_app_number] => 17/562729 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9907 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562729
Method for error handling of an interconnection protocol, controller and storage device Dec 26, 2021 Issued
Array ( [id] => 17535441 [patent_doc_number] => 20220114050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SYSTEMS AND METHODS FOR AN ECC ARCHITECTURE WITH MEMORY MAPPING [patent_app_type] => utility [patent_app_number] => 17/555635 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555635 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555635
Systems and methods for an ECC architecture with memory mapping Dec 19, 2021 Issued
Array ( [id] => 18561629 [patent_doc_number] => 11726872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Systems and methods for an ECC architecture with memory mapping [patent_app_type] => utility [patent_app_number] => 17/555642 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6728 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555642
Systems and methods for an ECC architecture with memory mapping Dec 19, 2021 Issued
Array ( [id] => 18984328 [patent_doc_number] => 11909525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Communication system, communication method, and communication apparatus [patent_app_type] => utility [patent_app_number] => 17/542987 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5890 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542987 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542987
Communication system, communication method, and communication apparatus Dec 5, 2021 Issued
Array ( [id] => 18393435 [patent_doc_number] => 20230161655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => TRAINING AND USING A MEMORY FAILURE PREDICTION MODEL [patent_app_type] => utility [patent_app_number] => 17/531158 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531158
Training and using a memory failure prediction model Nov 18, 2021 Issued
Array ( [id] => 17432594 [patent_doc_number] => 20220060304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => CODE BLOCK GROUPING AND FEEDBACK THAT SUPPORT EFFICIENT RETRANSMISSIONS [patent_app_type] => utility [patent_app_number] => 17/454017 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454017
Code block grouping and feedback that support efficient retransmissions Nov 7, 2021 Issued
Array ( [id] => 17403604 [patent_doc_number] => 20220045695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/509570 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509570 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509570
Transmitter and parity permutation method thereof Oct 24, 2021 Issued
Array ( [id] => 18494590 [patent_doc_number] => 11700015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 64-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 17/500848 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5830 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500848
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 64-symbol mapping, and bit interleaving method using same Oct 12, 2021 Issued
Array ( [id] => 18279382 [patent_doc_number] => 20230094854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => Phased Parameterized Combinatoric Testing for a Data Storage System [patent_app_type] => utility [patent_app_number] => 17/491080 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491080
Phased parameterized combinatoric testing for a data storage system Sep 29, 2021 Issued
Array ( [id] => 19028277 [patent_doc_number] => 11927629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Global time counter based debug [patent_app_type] => utility [patent_app_number] => 17/486675 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486675
Global time counter based debug Sep 26, 2021 Issued
Array ( [id] => 18790317 [patent_doc_number] => 20230379127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => COMMUNICATIONS DEVICE, INFRASTRUCTURE EQUIPMENT AND METHODS [patent_app_type] => utility [patent_app_number] => 18/031014 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18031014 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/031014
Communications device, infrastructure equipment and methods Sep 21, 2021 Issued
Array ( [id] => 19080049 [patent_doc_number] => 11949435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Markov encoder-decoder optimized for cyclo-stationary communications channel or storage media [patent_app_type] => utility [patent_app_number] => 17/475552 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475552 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/475552
Markov encoder-decoder optimized for cyclo-stationary communications channel or storage media Sep 14, 2021 Issued
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