![](/images/general/no_picture/200_user.png)
Rutao Wu
Supervisory Patent Examiner (ID: 2531, Phone: (571)272-3136 , Office: P/3621 )
Most Active Art Unit | 3628 |
Art Unit(s) | 3621, 3623, 3628, 3639 |
Total Applications | 283 |
Issued Applications | 100 |
Pending Applications | 11 |
Abandoned Applications | 172 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 10199169
[patent_doc_number] => 20150084155
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-26
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/555138
[patent_app_country] => US
[patent_app_date] => 2014-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2903
[patent_no_of_claims] => 6
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555138
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/555138 | Semiconductor device and method of fabricating the same | Nov 25, 2014 | Issued |
Array
(
[id] => 9931552
[patent_doc_number] => 20150079744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-19
[patent_title] => 'SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/550351
[patent_app_country] => US
[patent_app_date] => 2014-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 10858
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14550351
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/550351 | Semiconductor device with buried bit line and method for fabricating the same | Nov 20, 2014 | Issued |
Array
(
[id] => 11043415
[patent_doc_number] => 20160240371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-18
[patent_title] => 'PROTECTION METHOD FOR PROTECTING A SILICIDE LAYER'
[patent_app_type] => utility
[patent_app_number] => 15/029148
[patent_app_country] => US
[patent_app_date] => 2014-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3065
[patent_no_of_claims] => 16
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15029148
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/029148 | Protection method for protecting a silicide layer | Nov 18, 2014 | Issued |
Array
(
[id] => 10106900
[patent_doc_number] => 09142683
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-22
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/540167
[patent_app_country] => US
[patent_app_date] => 2014-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 50
[patent_no_of_words] => 32742
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14540167
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/540167 | Semiconductor device and manufacturing method thereof | Nov 12, 2014 | Issued |
Array
(
[id] => 11925851
[patent_doc_number] => 09793442
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-17
[patent_title] => 'Optoelectronic component'
[patent_app_type] => utility
[patent_app_number] => 15/034017
[patent_app_country] => US
[patent_app_date] => 2014-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 3736
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15034017
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/034017 | Optoelectronic component | Nov 3, 2014 | Issued |
Array
(
[id] => 10238079
[patent_doc_number] => 20150123073
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-07
[patent_title] => 'High Temperature Sensor Selective for Propane and Other Reducing Gases'
[patent_app_type] => utility
[patent_app_number] => 14/532521
[patent_app_country] => US
[patent_app_date] => 2014-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 16127
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532521
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/532521 | High temperature sensor selective for propane and other reducing gases | Nov 3, 2014 | Issued |
Array
(
[id] => 11071497
[patent_doc_number] => 20160268461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-15
[patent_title] => 'INFRARED DETECTION ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 15/033945
[patent_app_country] => US
[patent_app_date] => 2014-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 5176
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033945
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/033945 | Infrared detection element | Oct 30, 2014 | Issued |
Array
(
[id] => 10184678
[patent_doc_number] => 09214358
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-12-15
[patent_title] => 'Equal gate height control method for semiconductor device with different pattern densites'
[patent_app_type] => utility
[patent_app_number] => 14/527848
[patent_app_country] => US
[patent_app_date] => 2014-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 6246
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14527848
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/527848 | Equal gate height control method for semiconductor device with different pattern densites | Oct 29, 2014 | Issued |
Array
(
[id] => 10583751
[patent_doc_number] => 09305877
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-04-05
[patent_title] => '3D package with through substrate vias'
[patent_app_type] => utility
[patent_app_number] => 14/528765
[patent_app_country] => US
[patent_app_date] => 2014-10-30
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/528765 | 3D package with through substrate vias | Oct 29, 2014 | Issued |
Array
(
[id] => 10502393
[patent_doc_number] => 09230795
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-01-05
[patent_title] => 'Directional pre-clean in silicide and contact formation'
[patent_app_type] => utility
[patent_app_number] => 14/527300
[patent_app_country] => US
[patent_app_date] => 2014-10-29
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14527300
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/527300 | Directional pre-clean in silicide and contact formation | Oct 28, 2014 | Issued |
Array
(
[id] => 10417891
[patent_doc_number] => 20150302900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-22
[patent_title] => 'SEMICONDUCTOR STACKED PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 14/526802
[patent_app_country] => US
[patent_app_date] => 2014-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14526802
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/526802 | Semiconductor stacked package | Oct 28, 2014 | Issued |
Array
(
[id] => 10624424
[patent_doc_number] => 09343374
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-05-17
[patent_title] => 'Efficient main spacer pull back process for advanced VLSI CMOS technologies'
[patent_app_type] => utility
[patent_app_number] => 14/527207
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/527207 | Efficient main spacer pull back process for advanced VLSI CMOS technologies | Oct 28, 2014 | Issued |
Array
(
[id] => 9864772
[patent_doc_number] => 20150044791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'ORGANIC LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING'
[patent_app_type] => utility
[patent_app_number] => 14/525720
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/525720 | Organic light emitting diode and method of manufacturing | Oct 27, 2014 | Issued |
Array
(
[id] => 10217435
[patent_doc_number] => 20150102428
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-16
[patent_title] => 'MERGED FIN FINFET WITH (100) SIDEWALL SURFACES AND METHOD OF MAKING SAME'
[patent_app_type] => utility
[patent_app_number] => 14/524367
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14524367
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/524367 | MERGED FIN FINFET WITH (100) SIDEWALL SURFACES AND METHOD OF MAKING SAME | Oct 26, 2014 | Abandoned |
Array
(
[id] => 10433304
[patent_doc_number] => 20150318316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-05
[patent_title] => 'DISPLAY SUBSTRATE AND FABRICATING METHOD THEREOF, MASK PLATE, AND MASK PLATE GROUP'
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[patent_app_number] => 14/522528
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/522528 | Display substrate and fabricating method thereof, mask plate, and mask plate group | Oct 22, 2014 | Issued |
Array
(
[id] => 10557109
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[patent_issue_date] => 2016-03-08
[patent_title] => 'Non-volatile storage having oxide/nitride sidewall'
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[patent_app_number] => 14/511834
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Array
(
[id] => 10402710
[patent_doc_number] => 20150287718
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[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES'
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[patent_app_number] => 14/511532
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/511532 | Semiconductor integrated circuit devices | Oct 9, 2014 | Issued |
Array
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[patent_title] => 'Semiconductor element, method for manufacturing the semiconductor element, and semiconductor device including the semiconductor element'
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[patent_app_number] => 14/509310
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Array
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[patent_title] => 'Semiconductor device and electronic device'
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Array
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[patent_title] => 'Contact for high-k metal gate device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/507064 | Contact for high-k metal gate device | Oct 5, 2014 | Issued |