Search

Ryan A. Dare

Examiner (ID: 18932, Phone: (571)272-4069 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2186, 2132, 2136
Total Applications
695
Issued Applications
488
Pending Applications
70
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19017043 [patent_doc_number] => 11923992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G Ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 17/022075 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022075
Modular system (switch boards and mid-plane) for supporting 50G or 100G Ethernet speeds of FPGA+SSD Sep 14, 2020 Issued
Array ( [id] => 19017043 [patent_doc_number] => 11923992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Modular system (switch boards and mid-plane) for supporting 50G or 100G Ethernet speeds of FPGA+SSD [patent_app_type] => utility [patent_app_number] => 17/022075 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022075
Modular system (switch boards and mid-plane) for supporting 50G or 100G Ethernet speeds of FPGA+SSD Sep 14, 2020 Issued
Array ( [id] => 17636713 [patent_doc_number] => 11347437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Processor system having memory interleaving, and method for accessing interleaved memory banks with one clock cycle [patent_app_type] => utility [patent_app_number] => 17/018470 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3627 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018470
Processor system having memory interleaving, and method for accessing interleaved memory banks with one clock cycle Sep 10, 2020 Issued
Array ( [id] => 18697420 [patent_doc_number] => 20230327883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => VEHICLE BOOTLOADER AUTHENTICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/025093 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18025093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/025093
System method for vehicle bootloader image authentication using random number generator with cryptographic hash values Sep 9, 2020 Issued
Array ( [id] => 17084062 [patent_doc_number] => 20210279068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => MEMORY SYSTEM EXECUTING LOADING OF SOFTWARE AT STARTUP AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/014807 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014807
Memory system executing loading of software at startup and control method Sep 7, 2020 Issued
Array ( [id] => 16523902 [patent_doc_number] => 20200397982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SYSTEM AND METHOD FOR INSULIN PUMP MEDICAL DEVICE INCLUDING A SLIDER ASSEMBLY WHEREIN IMAGES ON DISPLAY ALLOW FOR HIGHLIGHTING AND MAGNIFYING IMAGES [patent_app_type] => utility [patent_app_number] => 17/012165 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/012165
System and method for insulin pump medical device including a slider assembly wherein images on display allow for highlighting and magnifying images Sep 3, 2020 Issued
Array ( [id] => 16903056 [patent_doc_number] => 20210181972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => APPARATUS AND METHOD FOR PROGRAMMING DATA OF PAGE GROUPS INTO FLASH UNITS [patent_app_type] => utility [patent_app_number] => 17/010420 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010420 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010420
Apparatus and method for programming user data on the pages and the parity of the page group into flash modules Sep 1, 2020 Issued
Array ( [id] => 18687096 [patent_doc_number] => 11782833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => System and method of determining available bandwidth in disaggregated tiered cache for cloud content storage [patent_app_type] => utility [patent_app_number] => 17/008509 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008509
System and method of determining available bandwidth in disaggregated tiered cache for cloud content storage Aug 30, 2020 Issued
Array ( [id] => 16818779 [patent_doc_number] => 11003609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Multi-protocol IO infrastructure for a flexible storage platform [patent_app_type] => utility [patent_app_number] => 16/994405 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7153 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994405 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994405
Multi-protocol IO infrastructure for a flexible storage platform Aug 13, 2020 Issued
Array ( [id] => 16675790 [patent_doc_number] => 20210064556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => PRE-PROCESSING OF DATA USING AUTONOMOUS MEMORY ACCESS AND RELATED SYSTEMS, METHODS, AND DEVICES [patent_app_type] => utility [patent_app_number] => 16/947688 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947688
Pre-processing of data using autonomous memory access and related systems, methods, and devices Aug 11, 2020 Issued
Array ( [id] => 17469223 [patent_doc_number] => 11275700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Integrated circuit I/O integrity and degradation monitoring [patent_app_type] => utility [patent_app_number] => 16/988993 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 11930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16988993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/988993
Integrated circuit I/O integrity and degradation monitoring Aug 9, 2020 Issued
Array ( [id] => 17069201 [patent_doc_number] => 20210271417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MEMORY DEVICE AND SCHEDULING METHOD FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/985240 [patent_app_country] => US [patent_app_date] => 2020-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16985240 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/985240
Memory device for scheduling maximum number of memory macros write operations at re-arranged time intervals Aug 4, 2020 Issued
Array ( [id] => 18030797 [patent_doc_number] => 11513986 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-29 [patent_title] => DMA engine that generates an address-less memory descriptor that does not include a memory address for communicating with integrated circuit device [patent_app_type] => utility [patent_app_number] => 16/983131 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11553 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983131
DMA engine that generates an address-less memory descriptor that does not include a memory address for communicating with integrated circuit device Aug 2, 2020 Issued
Array ( [id] => 17515542 [patent_doc_number] => 11294692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Basic input output system (BIOS)--identified memory size and node address range mirroring system [patent_app_type] => utility [patent_app_number] => 16/940098 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940098
Basic input output system (BIOS)--identified memory size and node address range mirroring system Jul 26, 2020 Issued
Array ( [id] => 17372117 [patent_doc_number] => 20220027169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => Application and Related Object Schematic Viewer [patent_app_type] => utility [patent_app_number] => 16/934356 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934356
Application and related object schematic viewer for software application change tracking and management Jul 20, 2020 Issued
Array ( [id] => 16559190 [patent_doc_number] => 20210004339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => Digital Interface Circuit for Analog-to-Digital Converter [patent_app_type] => utility [patent_app_number] => 16/933752 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933752
Digital interface circuit for sequencing analog-to-digital converter Jul 19, 2020 Issued
Array ( [id] => 16615912 [patent_doc_number] => 20210034565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => RECALIBRATION OF PHY CIRCUITRY FOR THE PCI EXPRESS (PIPE) INTERFACE BASED ON USING A MESSAGE BUS INTERFACE [patent_app_type] => utility [patent_app_number] => 16/926524 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926524
Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface Jul 9, 2020 Issued
Array ( [id] => 17252993 [patent_doc_number] => 11188482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Apparatus and method of zero-copy application co-processor with storage class memory [patent_app_type] => utility [patent_app_number] => 16/917392 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5449 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917392
Apparatus and method of zero-copy application co-processor with storage class memory Jun 29, 2020 Issued
Array ( [id] => 17352135 [patent_doc_number] => 11226772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-18 [patent_title] => Peak power reduction management in non-volatile storage by delaying start times operations [patent_app_type] => utility [patent_app_number] => 16/912381 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 17458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912381
Peak power reduction management in non-volatile storage by delaying start times operations Jun 24, 2020 Issued
Array ( [id] => 16844828 [patent_doc_number] => 11016917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Data storage system and method for multiple communication protocols and direct memory access [patent_app_type] => utility [patent_app_number] => 16/911312 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911312 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911312
Data storage system and method for multiple communication protocols and direct memory access Jun 23, 2020 Issued
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