
Ryan A. Dare
Examiner (ID: 9141, Phone: (571)272-4069 , Office: P/2136 )
| Most Active Art Unit | 2136 |
| Art Unit(s) | 2186, 2132, 2136 |
| Total Applications | 705 |
| Issued Applications | 493 |
| Pending Applications | 62 |
| Abandoned Applications | 154 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7690032
[patent_doc_number] => 20070234001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'DATA WRITING IN SYSTEM WITH ALIGNMENT RESTRICTION OR VECTOR-BASED SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 11/623466
[patent_app_country] => US
[patent_app_date] => 2007-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4283
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 26
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20070234001.pdf
[firstpage_image] =>[orig_patent_app_number] => 11623466
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/623466 | Data writing in system with alignment restriction or vector-based systems | Jan 15, 2007 | Issued |
Array
(
[id] => 7557418
[patent_doc_number] => 08069327
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-29
[patent_title] => 'Commands scheduled for frequency mismatch bubbles'
[patent_app_type] => utility
[patent_app_number] => 11/648341
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 5056
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/069/08069327.pdf
[firstpage_image] =>[orig_patent_app_number] => 11648341
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/648341 | Commands scheduled for frequency mismatch bubbles | Dec 27, 2006 | Issued |
Array
(
[id] => 5020837
[patent_doc_number] => 20070146803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Information recording apparatus and recorded information management method'
[patent_app_type] => utility
[patent_app_number] => 11/640354
[patent_app_country] => US
[patent_app_date] => 2006-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3690
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20070146803.pdf
[firstpage_image] =>[orig_patent_app_number] => 11640354
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/640354 | Information recording apparatus and recorded information management method | Dec 17, 2006 | Abandoned |
Array
(
[id] => 10536695
[patent_doc_number] => 09262326
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-16
[patent_title] => 'Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem'
[patent_app_type] => utility
[patent_app_number] => 11/565034
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4880
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11565034
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/565034 | Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem | Nov 29, 2006 | Issued |
Array
(
[id] => 4917591
[patent_doc_number] => 20080098192
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'METHODS OF REUSING LOG BLOCKS IN NON-VOLATILE MEMORIES AND RELATED NON-VOLATILE MEMORY DEVICES'
[patent_app_type] => utility
[patent_app_number] => 11/565009
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5904
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20080098192.pdf
[firstpage_image] =>[orig_patent_app_number] => 11565009
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/565009 | Methods of reusing log blocks in non-volatile memories and related non-volatile memory devices | Nov 29, 2006 | Issued |
Array
(
[id] => 4836526
[patent_doc_number] => 20080133847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'VOID EXTENT METHOD FOR DATA INTEGRITY ERROR HANDLING'
[patent_app_type] => utility
[patent_app_number] => 11/564896
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1676
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20080133847.pdf
[firstpage_image] =>[orig_patent_app_number] => 11564896
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/564896 | VOID EXTENT METHOD FOR DATA INTEGRITY ERROR HANDLING | Nov 29, 2006 | Abandoned |
Array
(
[id] => 4510765
[patent_doc_number] => 07949846
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-24
[patent_title] => 'Map shuffle-allocation map protection without extra I/O\'S using minimal extra disk space'
[patent_app_type] => utility
[patent_app_number] => 11/564868
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3481
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/949/07949846.pdf
[firstpage_image] =>[orig_patent_app_number] => 11564868
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/564868 | Map shuffle-allocation map protection without extra I/O'S using minimal extra disk space | Nov 29, 2006 | Issued |
Array
(
[id] => 4836507
[patent_doc_number] => 20080133836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR A DEFINED MULTILEVEL CACHE'
[patent_app_type] => utility
[patent_app_number] => 11/565340
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2965
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20080133836.pdf
[firstpage_image] =>[orig_patent_app_number] => 11565340
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/565340 | APPARATUS, SYSTEM, AND METHOD FOR A DEFINED MULTILEVEL CACHE | Nov 29, 2006 | Abandoned |
Array
(
[id] => 8678559
[patent_doc_number] => 08386694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-26
[patent_title] => 'Memory device, its access method, and memory system'
[patent_app_type] => utility
[patent_app_number] => 11/565276
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 7789
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11565276
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/565276 | Memory device, its access method, and memory system | Nov 29, 2006 | Issued |
Array
(
[id] => 8923901
[patent_doc_number] => 08489850
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-16
[patent_title] => 'Memory apparatus and memory control method'
[patent_app_type] => utility
[patent_app_number] => 11/565279
[patent_app_country] => US
[patent_app_date] => 2006-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 23
[patent_no_of_words] => 13395
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11565279
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/565279 | Memory apparatus and memory control method | Nov 29, 2006 | Issued |
Array
(
[id] => 9834458
[patent_doc_number] => 08943292
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-27
[patent_title] => 'System and method for memory array access with fast address decoder'
[patent_app_type] => utility
[patent_app_number] => 11/552817
[patent_app_country] => US
[patent_app_date] => 2006-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 9915
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11552817
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/552817 | System and method for memory array access with fast address decoder | Oct 24, 2006 | Issued |
Array
(
[id] => 5153116
[patent_doc_number] => 20070035998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'Nonvolatile memory apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/581690
[patent_app_country] => US
[patent_app_date] => 2006-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10254
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0035/20070035998.pdf
[firstpage_image] =>[orig_patent_app_number] => 11581690
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/581690 | Nonvolatile memory apparatus | Oct 16, 2006 | Abandoned |
Array
(
[id] => 4984214
[patent_doc_number] => 20070088773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-19
[patent_title] => 'Digital signal processing apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/549239
[patent_app_country] => US
[patent_app_date] => 2006-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 8685
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20070088773.pdf
[firstpage_image] =>[orig_patent_app_number] => 11549239
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/549239 | Digital signal processing apparatus | Oct 12, 2006 | Issued |
Array
(
[id] => 9187016
[patent_doc_number] => 08627002
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-07
[patent_title] => 'Method to increase performance of non-contiguously written sectors'
[patent_app_type] => utility
[patent_app_number] => 11/549038
[patent_app_country] => US
[patent_app_date] => 2006-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2907
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11549038
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/549038 | Method to increase performance of non-contiguously written sectors | Oct 11, 2006 | Issued |
Array
(
[id] => 4747307
[patent_doc_number] => 20080091909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'METHOD AND SYSTEM TO MANAGE VIRTUAL MACHINE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/548712
[patent_app_country] => US
[patent_app_date] => 2006-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8019
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20080091909.pdf
[firstpage_image] =>[orig_patent_app_number] => 11548712
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/548712 | METHOD AND SYSTEM TO MANAGE VIRTUAL MACHINE MEMORY | Oct 11, 2006 | Abandoned |
Array
(
[id] => 4747281
[patent_doc_number] => 20080091883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'Load starvation detector and buster'
[patent_app_type] => utility
[patent_app_number] => 11/548820
[patent_app_country] => US
[patent_app_date] => 2006-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2309
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20080091883.pdf
[firstpage_image] =>[orig_patent_app_number] => 11548820
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/548820 | Load starvation detector and buster | Oct 11, 2006 | Abandoned |
Array
(
[id] => 4747277
[patent_doc_number] => 20080091879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'Method and structure for interruting L2 cache live-lock occurrences'
[patent_app_type] => utility
[patent_app_number] => 11/548829
[patent_app_country] => US
[patent_app_date] => 2006-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4290
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20080091879.pdf
[firstpage_image] =>[orig_patent_app_number] => 11548829
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/548829 | Method and structure for interruting L2 cache live-lock occurrences | Oct 11, 2006 | Abandoned |
Array
(
[id] => 4747299
[patent_doc_number] => 20080091901
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'Method for non-volatile memory with worst-case control data management'
[patent_app_type] => utility
[patent_app_number] => 11/549035
[patent_app_country] => US
[patent_app_date] => 2006-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 47
[patent_no_of_words] => 30170
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20080091901.pdf
[firstpage_image] =>[orig_patent_app_number] => 11549035
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/549035 | Method for non-volatile memory with worst-case control data management | Oct 11, 2006 | Abandoned |
Array
(
[id] => 4747269
[patent_doc_number] => 20080091871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'Non-volatile memory with worst-case control data management'
[patent_app_type] => utility
[patent_app_number] => 11/549040
[patent_app_country] => US
[patent_app_date] => 2006-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 47
[patent_no_of_words] => 30169
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20080091871.pdf
[firstpage_image] =>[orig_patent_app_number] => 11549040
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/549040 | Non-volatile memory with worst-case control data management | Oct 11, 2006 | Abandoned |
Array
(
[id] => 4747306
[patent_doc_number] => 20080091908
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'Speed selective table scan operation'
[patent_app_type] => utility
[patent_app_number] => 11/548889
[patent_app_country] => US
[patent_app_date] => 2006-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8144
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20080091908.pdf
[firstpage_image] =>[orig_patent_app_number] => 11548889
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/548889 | Speed selective table scan operation | Oct 11, 2006 | Issued |