Search

Ryan A. Dare

Examiner (ID: 18932, Phone: (571)272-4069 , Office: P/2136 )

Most Active Art Unit
2136
Art Unit(s)
2186, 2132, 2136
Total Applications
695
Issued Applications
488
Pending Applications
70
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19933559 [patent_doc_number] => 12306763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Systems and methods for streaming storage device content [patent_app_type] => utility [patent_app_number] => 17/856918 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856918 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856918
Systems and methods for streaming storage device content Jun 30, 2022 Issued
Array ( [id] => 19933559 [patent_doc_number] => 12306763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Systems and methods for streaming storage device content [patent_app_type] => utility [patent_app_number] => 17/856918 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856918 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856918
Systems and methods for streaming storage device content Jun 30, 2022 Issued
Array ( [id] => 18839393 [patent_doc_number] => 11847467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Boot method for embedded system including first and second baseboard management controller (BMC) and operating system (OS) image file using shared non-volatile memory module [patent_app_type] => utility [patent_app_number] => 17/853202 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3111 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 408 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853202
Boot method for embedded system including first and second baseboard management controller (BMC) and operating system (OS) image file using shared non-volatile memory module Jun 28, 2022 Issued
Array ( [id] => 19383042 [patent_doc_number] => 20240272912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => DISC LOADING CONTROL METHOD, APPARATUS, AND DEVICE, AND READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/567652 [patent_app_country] => US [patent_app_date] => 2022-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18567652 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/567652
Disc loading control method, apparatus, and device, and readable storage medium Jun 18, 2022 Issued
Array ( [id] => 19703887 [patent_doc_number] => 12197923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Supporting different security schemes after power cycle with different boot personalities for network devices [patent_app_type] => utility [patent_app_number] => 17/843024 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5054 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843024
Supporting different security schemes after power cycle with different boot personalities for network devices Jun 16, 2022 Issued
Array ( [id] => 19669827 [patent_doc_number] => 12182586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-31 [patent_title] => System and method for microlocation-based with tokenized virtual dynamic software applications (app) experiences [patent_app_type] => utility [patent_app_number] => 17/805892 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805892
System and method for microlocation-based with tokenized virtual dynamic software applications (app) experiences Jun 7, 2022 Issued
Array ( [id] => 17884966 [patent_doc_number] => 20220300443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => PRE-PROCESSING OF WAVEFORM DATA USING AUTONOMOUS WAVEFORM CIRCUITRY AND RELATED APPARATUSES AND METHODS [patent_app_type] => utility [patent_app_number] => 17/805642 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805642
Pre-processing of waveform data using autonomous waveform circuitry and related apparatuses and methods Jun 5, 2022 Issued
Array ( [id] => 19014627 [patent_doc_number] => 11921556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Device maintenance of a data storage device including wear levelling, garbage collection, or combination thereof [patent_app_type] => utility [patent_app_number] => 17/832344 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832344
Device maintenance of a data storage device including wear levelling, garbage collection, or combination thereof Jun 2, 2022 Issued
Array ( [id] => 17853923 [patent_doc_number] => 20220283965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => MEMORY DEVICE INTERFACE WITH A DEDICATED PORTION FOR COMMAND PROCESSING [patent_app_type] => utility [patent_app_number] => 17/825632 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825632
Memory device interface communicating with set of data bursts corresponding to memory dies via dedicated portions for command processing May 25, 2022 Issued
Array ( [id] => 19576524 [patent_doc_number] => 20240380816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => METHOD FOR TIME-OF-FLIGHT-BASED CONFIGURATION OF A DEVICE-INTERNAL SIGNAL TRANSMISSION IN A CONTROL DEVICE, AND CORRESPONDINGLY OPERABLE CONTROL DEVICE AND MOTOR VEHICLE [patent_app_type] => utility [patent_app_number] => 18/565908 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18565908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/565908
Method for runtime-based configuration of a device-internal signal transmission in a control device, and correspondingly operable control device and motor vehicle May 19, 2022 Issued
Array ( [id] => 18911711 [patent_doc_number] => 11874689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller [patent_app_type] => utility [patent_app_number] => 17/749133 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 20018 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749133
Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller May 18, 2022 Issued
Array ( [id] => 18911711 [patent_doc_number] => 11874689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller [patent_app_type] => utility [patent_app_number] => 17/749133 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 20018 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749133
Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller May 18, 2022 Issued
Array ( [id] => 18911711 [patent_doc_number] => 11874689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller [patent_app_type] => utility [patent_app_number] => 17/749133 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 20018 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749133
Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller May 18, 2022 Issued
Array ( [id] => 18911711 [patent_doc_number] => 11874689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller [patent_app_type] => utility [patent_app_number] => 17/749133 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 20018 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749133
Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller May 18, 2022 Issued
Array ( [id] => 19327942 [patent_doc_number] => 12045630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Customizable initialization orchestration module providing a graphical preview of a graphical status screen user interface [patent_app_type] => utility [patent_app_number] => 17/663112 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16481 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663112 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663112
Customizable initialization orchestration module providing a graphical preview of a graphical status screen user interface May 11, 2022 Issued
Array ( [id] => 18136021 [patent_doc_number] => 11561697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Disaggregated memory server having chassis with a plurality of receptacles accessible configured to convey data with PCIE bus and plurality of memory banks [patent_app_type] => utility [patent_app_number] => 17/743277 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 13817 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743277
Disaggregated memory server having chassis with a plurality of receptacles accessible configured to convey data with PCIE bus and plurality of memory banks May 11, 2022 Issued
Array ( [id] => 18703381 [patent_doc_number] => 11789892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface [patent_app_type] => utility [patent_app_number] => 17/738625 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 21265 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738625
Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface May 5, 2022 Issued
Array ( [id] => 17794000 [patent_doc_number] => 20220253092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => HOST DEVICE, SLAVE DEVICE, AND DATA TRANSFER SYSTEM [patent_app_type] => utility [patent_app_number] => 17/729520 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729520
Host device connected to slave device and data transfer system wherein voltage levels are driven high or low based on a plurality of clock signals Apr 25, 2022 Issued
Array ( [id] => 19739931 [patent_doc_number] => 12216764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Smart network interface controller certificate management [patent_app_type] => utility [patent_app_number] => 17/728597 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4658 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728597
Smart network interface controller certificate management Apr 24, 2022 Issued
Array ( [id] => 18912065 [patent_doc_number] => 11875044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Direct memory access using joint test action group (JTAG) cells addressing [patent_app_type] => utility [patent_app_number] => 17/722854 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722854
Direct memory access using joint test action group (JTAG) cells addressing Apr 17, 2022 Issued
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