
Ryan A. Doyle
Examiner (ID: 11119)
| Most Active Art Unit | 3637 |
| Art Unit(s) | 4128, 3637 |
| Total Applications | 240 |
| Issued Applications | 142 |
| Pending Applications | 1 |
| Abandoned Applications | 97 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1150172
[patent_doc_number] => 06782526
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'Photomask designing method, a photomask designing apparatus, a computer readable storage medium, a photomask, a photoresist, photosensitive resin, a base plate, a microlens, and an optical element'
[patent_app_type] => B2
[patent_app_number] => 10/335932
[patent_app_country] => US
[patent_app_date] => 2003-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 26
[patent_no_of_words] => 12097
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/782/06782526.pdf
[firstpage_image] =>[orig_patent_app_number] => 10335932
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/335932 | Photomask designing method, a photomask designing apparatus, a computer readable storage medium, a photomask, a photoresist, photosensitive resin, a base plate, a microlens, and an optical element | Jan 2, 2003 | Issued |
Array
(
[id] => 1249013
[patent_doc_number] => 06678875
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-13
[patent_title] => 'Self-contained embedded test design environment and environment setup utility'
[patent_app_type] => B2
[patent_app_number] => 10/323979
[patent_app_country] => US
[patent_app_date] => 2002-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 8143
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/678/06678875.pdf
[firstpage_image] =>[orig_patent_app_number] => 10323979
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/323979 | Self-contained embedded test design environment and environment setup utility | Dec 19, 2002 | Issued |
Array
(
[id] => 6853094
[patent_doc_number] => 20030145297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-31
[patent_title] => 'Method and program product for completing a circuit design having embedded test structures'
[patent_app_type] => new
[patent_app_number] => 10/323815
[patent_app_country] => US
[patent_app_date] => 2002-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4262
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20030145297.pdf
[firstpage_image] =>[orig_patent_app_number] => 10323815
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/323815 | Method and program product for completing a circuit design having embedded test structures | Dec 19, 2002 | Issued |
Array
(
[id] => 1218380
[patent_doc_number] => 06711718
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-23
[patent_title] => 'Parallel electronic design automation: distributed simultaneous editing'
[patent_app_type] => B2
[patent_app_number] => 10/269525
[patent_app_country] => US
[patent_app_date] => 2002-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5438
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/711/06711718.pdf
[firstpage_image] =>[orig_patent_app_number] => 10269525
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/269525 | Parallel electronic design automation: distributed simultaneous editing | Oct 9, 2002 | Issued |
Array
(
[id] => 7625667
[patent_doc_number] => 06769100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-27
[patent_title] => 'Method and system for power node current waveform modeling'
[patent_app_type] => B2
[patent_app_number] => 10/242235
[patent_app_country] => US
[patent_app_date] => 2002-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2515
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 4
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/769/06769100.pdf
[firstpage_image] =>[orig_patent_app_number] => 10242235
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/242235 | Method and system for power node current waveform modeling | Sep 11, 2002 | Issued |
Array
(
[id] => 1241009
[patent_doc_number] => 06691285
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-10
[patent_title] => 'Exponential increments in FET size selection'
[patent_app_type] => B1
[patent_app_number] => 10/229535
[patent_app_country] => US
[patent_app_date] => 2002-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1598
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/691/06691285.pdf
[firstpage_image] =>[orig_patent_app_number] => 10229535
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/229535 | Exponential increments in FET size selection | Aug 26, 2002 | Issued |
Array
(
[id] => 7271501
[patent_doc_number] => 20040060019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'METHOD AND APPARATUS FOR HIERARCHICAL CLOCK TREE ANALYSIS'
[patent_app_type] => new
[patent_app_number] => 10/215125
[patent_app_country] => US
[patent_app_date] => 2002-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4179
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20040060019.pdf
[firstpage_image] =>[orig_patent_app_number] => 10215125
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/215125 | Method and apparatus for hierarchical clock tree analysis | Aug 7, 2002 | Issued |
Array
(
[id] => 7458345
[patent_doc_number] => 20040010769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-15
[patent_title] => 'Method for reducing a pitch of a procedure'
[patent_app_type] => new
[patent_app_number] => 10/193225
[patent_app_country] => US
[patent_app_date] => 2002-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3849
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20040010769.pdf
[firstpage_image] =>[orig_patent_app_number] => 10193225
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/193225 | Method for reducing a pitch of a procedure | Jul 11, 2002 | Abandoned |
Array
(
[id] => 5910695
[patent_doc_number] => 20020144228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Method and apparatus for designing printed-circuit board'
[patent_app_type] => new
[patent_app_number] => 10/155115
[patent_app_country] => US
[patent_app_date] => 2002-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7985
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0144/20020144228.pdf
[firstpage_image] =>[orig_patent_app_number] => 10155115
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/155115 | Method and apparatus for designing printed-circuit board | May 27, 2002 | Issued |
Array
(
[id] => 1229645
[patent_doc_number] => 06701494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-02
[patent_title] => 'Method of using testbench tests to avoid task collisions in hardware description language'
[patent_app_type] => B2
[patent_app_number] => 10/137846
[patent_app_country] => US
[patent_app_date] => 2002-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1601
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/701/06701494.pdf
[firstpage_image] =>[orig_patent_app_number] => 10137846
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/137846 | Method of using testbench tests to avoid task collisions in hardware description language | Apr 30, 2002 | Issued |
Array
(
[id] => 6732086
[patent_doc_number] => 20030188276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'METHOD AND APPARATUS FOR IDENTIFYING SWITCHING RACE CONDITIONS IN A CIRCUIT DESIGN'
[patent_app_type] => new
[patent_app_number] => 10/114545
[patent_app_country] => US
[patent_app_date] => 2002-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4038
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20030188276.pdf
[firstpage_image] =>[orig_patent_app_number] => 10114545
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/114545 | Method and apparatus for identifying switching race conditions in a circuit design | Apr 1, 2002 | Issued |
Array
(
[id] => 1249020
[patent_doc_number] => 06678878
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-13
[patent_title] => 'Intelligent milling path creation for panelization abstract'
[patent_app_type] => B2
[patent_app_number] => 10/090645
[patent_app_country] => US
[patent_app_date] => 2002-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 6157
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/678/06678878.pdf
[firstpage_image] =>[orig_patent_app_number] => 10090645
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/090645 | Intelligent milling path creation for panelization abstract | Mar 3, 2002 | Issued |
Array
(
[id] => 6844609
[patent_doc_number] => 20030149956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-07
[patent_title] => 'Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography'
[patent_app_type] => new
[patent_app_number] => 10/061615
[patent_app_country] => US
[patent_app_date] => 2002-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2777
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0149/20030149956.pdf
[firstpage_image] =>[orig_patent_app_number] => 10061615
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/061615 | Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography | Jan 31, 2002 | Issued |
Array
(
[id] => 1170681
[patent_doc_number] => 06766497
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-20
[patent_title] => 'Method and system for reproduction in a genetic optimization process'
[patent_app_type] => B2
[patent_app_number] => 10/057245
[patent_app_country] => US
[patent_app_date] => 2002-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 2744
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/766/06766497.pdf
[firstpage_image] =>[orig_patent_app_number] => 10057245
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/057245 | Method and system for reproduction in a genetic optimization process | Jan 24, 2002 | Issued |
Array
(
[id] => 1229626
[patent_doc_number] => 06701492
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-02
[patent_title] => 'Method for the determination of resistances and capacitances of a circuit diagram, which represents an electrical circuit'
[patent_app_type] => B2
[patent_app_number] => 10/057125
[patent_app_country] => US
[patent_app_date] => 2002-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2454
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/701/06701492.pdf
[firstpage_image] =>[orig_patent_app_number] => 10057125
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/057125 | Method for the determination of resistances and capacitances of a circuit diagram, which represents an electrical circuit | Jan 24, 2002 | Issued |
Array
(
[id] => 1241030
[patent_doc_number] => 06691294
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-10
[patent_title] => 'Method and device for implementing by-pass capacitors'
[patent_app_type] => B2
[patent_app_number] => 10/055835
[patent_app_country] => US
[patent_app_date] => 2002-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3121
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/691/06691294.pdf
[firstpage_image] =>[orig_patent_app_number] => 10055835
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/055835 | Method and device for implementing by-pass capacitors | Jan 22, 2002 | Issued |
Array
(
[id] => 7622273
[patent_doc_number] => 06687893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-03
[patent_title] => 'Method and apparatus for pre-computing routes for multiple wiring models'
[patent_app_type] => B2
[patent_app_number] => 10/041942
[patent_app_country] => US
[patent_app_date] => 2002-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 74
[patent_figures_cnt] => 97
[patent_no_of_words] => 44982
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/687/06687893.pdf
[firstpage_image] =>[orig_patent_app_number] => 10041942
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/041942 | Method and apparatus for pre-computing routes for multiple wiring models | Jan 6, 2002 | Issued |
Array
(
[id] => 6746760
[patent_doc_number] => 20030023943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-30
[patent_title] => 'Method and apparatus for producing sub-optimal routes for a net by generating fake configurations'
[patent_app_type] => new
[patent_app_number] => 10/040954
[patent_app_country] => US
[patent_app_date] => 2002-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 75
[patent_figures_cnt] => 75
[patent_no_of_words] => 45751
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20030023943.pdf
[firstpage_image] =>[orig_patent_app_number] => 10040954
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/040954 | Method and apparatus for producing sub-optimal routes for a net by generating fake configurations | Jan 4, 2002 | Issued |
Array
(
[id] => 6749307
[patent_doc_number] => 20030043827
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'LP method and apparatus for identifying route propagations'
[patent_app_type] => new
[patent_app_number] => 10/040953
[patent_app_country] => US
[patent_app_date] => 2002-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 75
[patent_figures_cnt] => 75
[patent_no_of_words] => 45744
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20030043827.pdf
[firstpage_image] =>[orig_patent_app_number] => 10040953
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/040953 | LP method and apparatus for identifying route propagations | Jan 4, 2002 | Issued |
Array
(
[id] => 1186503
[patent_doc_number] => 06742170
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-25
[patent_title] => 'Repeatable swizzling patterns for capacitive and inductive noise cancellation'
[patent_app_type] => B2
[patent_app_number] => 10/040735
[patent_app_country] => US
[patent_app_date] => 2001-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 31
[patent_no_of_words] => 13162
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/742/06742170.pdf
[firstpage_image] =>[orig_patent_app_number] => 10040735
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/040735 | Repeatable swizzling patterns for capacitive and inductive noise cancellation | Dec 27, 2001 | Issued |