Ryan Bertram

Array ( [id] => 5166998 [patent_doc_number] => 20070288587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Transactional shared memory system and method of control' [patent_app_type] => utility [patent_app_number] => 11/450987 [patent_app_country] => US [patent_app_date] => 2006-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7653 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288587.pdf [firstpage_image] =>[orig_patent_app_number] => 11450987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5559982 [patent_doc_number] => 20090271559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'Method for Storing Individual Data Items of a Low-Voltage Switch' [patent_app_type] => utility [patent_app_number] => 11/887417 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1445 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20090271559.pdf [firstpage_image] =>[orig_patent_app_number] => 11887417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4440839 [patent_doc_number] => 07971000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Method and system for maintaining consistency of a cache memory accessible by multiple independent processes' [patent_app_type] => utility [patent_app_number] => 11/886514 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6323 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971000.pdf [firstpage_image] =>[orig_patent_app_number] => 11886514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5761678 [patent_doc_number] => 20060212623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Data control apparatus' [patent_app_type] => utility [patent_app_number] => 11/367306 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3340 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20060212623.pdf [firstpage_image] =>[orig_patent_app_number] => 11367306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5173523 [patent_doc_number] => 20070073962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Accessing device' [patent_app_type] => utility [patent_app_number] => 11/366944 [patent_app_country] => US [patent_app_date] => 2006-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4947 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20070073962.pdf [firstpage_image] =>[orig_patent_app_number] => 11366944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5132512 [patent_doc_number] => 20070208909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Scaled coercion of disk drive capacity' [patent_app_type] => utility [patent_app_number] => 11/366921 [patent_app_country] => US [patent_app_date] => 2006-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3334 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20070208909.pdf [firstpage_image] =>[orig_patent_app_number] => 11366921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5788949 [patent_doc_number] => 20060206704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Data transmission system and method for operating a data transmission system' [patent_app_type] => utility [patent_app_number] => 11/364819 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2815 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20060206704.pdf [firstpage_image] =>[orig_patent_app_number] => 11364819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 589986 [patent_doc_number] => 07464226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Fractional caching' [patent_app_type] => utility [patent_app_number] => 11/360778 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7988 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464226.pdf [firstpage_image] =>[orig_patent_app_number] => 11360778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5114858 [patent_doc_number] => 20070198774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Method and apparatus for implementing feedback directed deferral of nonessential DASD operations' [patent_app_type] => utility [patent_app_number] => 11/360349 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2282 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198774.pdf [firstpage_image] =>[orig_patent_app_number] => 11360349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 593395 [patent_doc_number] => 07461216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Memory controller' [patent_app_type] => utility [patent_app_number] => 11/359501 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4238 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461216.pdf [firstpage_image] =>[orig_patent_app_number] => 11359501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 290396 [patent_doc_number] => 07549021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Enhanced data integrity using parallel volatile and non-volatile transfer buffers' [patent_app_type] => utility [patent_app_number] => 11/359348 [patent_app_country] => US [patent_app_date] => 2006-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5241 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/549/07549021.pdf [firstpage_image] =>[orig_patent_app_number] => 11359348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9116157 [patent_doc_number] => 08572349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Processor with programmable configuration of logical-to-physical address translation on a per-client basis' [patent_app_type] => utility [patent_app_number] => 11/343698 [patent_app_country] => US [patent_app_date] => 2006-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4760 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11343698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9012393 [patent_doc_number] => 08527713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Cache locking without interference from normal allocations' [patent_app_type] => utility [patent_app_number] => 11/343765 [patent_app_country] => US [patent_app_date] => 2006-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2313 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11343765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9135 [patent_doc_number] => 07814282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Memory share by a plurality of processors' [patent_app_type] => utility [patent_app_number] => 11/908585 [patent_app_country] => US [patent_app_date] => 2006-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5289 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/814/07814282.pdf [firstpage_image] =>[orig_patent_app_number] => 11908585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4990658 [patent_doc_number] => 20070156999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Identifier associated with memory locations for managing memory accesses' [patent_app_type] => utility [patent_app_number] => 11/322669 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5854 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20070156999.pdf [firstpage_image] =>[orig_patent_app_number] => 11322669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5024700 [patent_doc_number] => 20070150667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Multiported memory with ports mapped to bank sets' [patent_app_type] => utility [patent_app_number] => 11/317757 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3265 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150667.pdf [firstpage_image] =>[orig_patent_app_number] => 11317757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5024704 [patent_doc_number] => 20070150671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Supporting macro memory instructions' [patent_app_type] => utility [patent_app_number] => 11/318238 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9378 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150671.pdf [firstpage_image] =>[orig_patent_app_number] => 11318238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 166620 [patent_doc_number] => 07673111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Memory system with both single and consolidated commands' [patent_app_type] => utility [patent_app_number] => 11/318028 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4424 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673111.pdf [firstpage_image] =>[orig_patent_app_number] => 11318028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4874783 [patent_doc_number] => 20080201517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Method for the conversion of Logical Into Real Block Addresses in Flash Memories' [patent_app_type] => utility [patent_app_number] => 11/813548 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1976 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201517.pdf [firstpage_image] =>[orig_patent_app_number] => 11813548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5108713 [patent_doc_number] => 20070067591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Storage control system' [patent_app_type] => utility [patent_app_number] => 11/289608 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8223 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20070067591.pdf [firstpage_image] =>[orig_patent_app_number] => 11289608 [rel_patent_id] =>[rel_patent_doc_number] =>)