Search

Ryan C. Jager

Examiner (ID: 6118, Phone: (571)272-7016 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2816, 2842
Total Applications
1378
Issued Applications
1224
Pending Applications
58
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20589083 [patent_doc_number] => 20260074680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => High-Side Switch System, Method for Controlling the Same, Integrated Circuit Chip, and Electronic Device [patent_app_type] => utility [patent_app_number] => 19/034548 [patent_app_country] => US [patent_app_date] => 2025-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19034548 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/034548
High-Side Switch System, Method for Controlling the Same, Integrated Circuit Chip, and Electronic Device Jan 21, 2025 Pending
Array ( [id] => 20124980 [patent_doc_number] => 20250240011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => ELECTRONIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/986704 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18986704 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/986704
ELECTRONIC CIRCUIT Dec 18, 2024 Pending
Array ( [id] => 19999837 [patent_doc_number] => 20250138059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => VOLTAGE DROOP DETECTION [patent_app_type] => utility [patent_app_number] => 18/925346 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925346 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/925346
VOLTAGE DROOP DETECTION Oct 23, 2024 Pending
Array ( [id] => 20312547 [patent_doc_number] => 20250330176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => CLOCK TRANSMISSION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/918069 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18918069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/918069
CLOCK TRANSMISSION CIRCUIT Oct 16, 2024 Pending
Array ( [id] => 20448971 [patent_doc_number] => 20260005697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => AVERAGING A DIGITAL PHASE LOCKED LOOP OUTPUT FREQUENCY TO CALCULATE A PRESET VALUE FOR USE IN THE EVENT OF A LINK LOSS [patent_app_type] => utility [patent_app_number] => 18/895490 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18895490 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/895490
AVERAGING A DIGITAL PHASE LOCKED LOOP OUTPUT FREQUENCY TO CALCULATE A PRESET VALUE FOR USE IN THE EVENT OF A LINK LOSS Sep 24, 2024 Pending
Array ( [id] => 20637028 [patent_doc_number] => 12597917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Power switch with normally on transistor [patent_app_type] => utility [patent_app_number] => 18/882850 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882850 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882850
POWER SWITCH WITH NORMALLY ON TRANSISTOR Sep 11, 2024 Issued
Array ( [id] => 19851454 [patent_doc_number] => 20250096805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => CHARGE PUMP CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/828011 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828011 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/828011
CHARGE PUMP CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT Sep 8, 2024 Pending
Array ( [id] => 20382016 [patent_doc_number] => 20250364509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/828516 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828516 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/828516
Semiconductor device Sep 8, 2024 Issued
Array ( [id] => 19635365 [patent_doc_number] => 20240413814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => OSCILLATING SIGNAL GENERATING CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/810138 [patent_app_country] => US [patent_app_date] => 2024-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810138 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/810138
OSCILLATING SIGNAL GENERATING CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE SAME Aug 19, 2024 Issued
Array ( [id] => 20544988 [patent_doc_number] => 20260051881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-19 [patent_title] => CLOCK PHASE TUNER EMPLOYING SET OF CONFIGURABLE SWITCHED-CURRENT UNIT CELLS [patent_app_type] => utility [patent_app_number] => 18/807335 [patent_app_country] => US [patent_app_date] => 2024-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18807335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/807335
CLOCK PHASE TUNER EMPLOYING SET OF CONFIGURABLE SWITCHED-CURRENT UNIT CELLS Aug 15, 2024 Pending
Array ( [id] => 20291888 [patent_doc_number] => 20250317131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => RECEIVER CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/805262 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805262 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/805262
RECEIVER CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME Aug 13, 2024 Pending
Array ( [id] => 20502330 [patent_doc_number] => 20260031793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => GLITCH FILTER CIRCUITRY FOR DEVICE-TO-DEVICE COMMUNICATION SYSTEM INTERFACE [patent_app_type] => utility [patent_app_number] => 18/783174 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783174 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783174
GLITCH FILTER CIRCUITRY FOR DEVICE-TO-DEVICE COMMUNICATION SYSTEM INTERFACE Jul 23, 2024 Pending
Array ( [id] => 20251772 [patent_doc_number] => 20250300641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => INPUT BUFFER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/776866 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776866
INPUT BUFFER CIRCUIT Jul 17, 2024 Pending
Array ( [id] => 19560761 [patent_doc_number] => 20240372553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => METHODS AND APPARATUS TO DYNAMICALLY CORRECT TIME KEEPING ERRORS [patent_app_type] => utility [patent_app_number] => 18/773777 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773777
METHODS AND APPARATUS TO DYNAMICALLY CORRECT TIME KEEPING ERRORS Jul 15, 2024 Pending
Array ( [id] => 19774020 [patent_doc_number] => 20250055446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => QUADRATURE PHASE SHIFTED CLOCK GENERATION WITH DUTY CYCLE CORRECTION [patent_app_type] => utility [patent_app_number] => 18/771327 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771327
QUADRATURE PHASE SHIFTED CLOCK GENERATION WITH DUTY CYCLE CORRECTION Jul 11, 2024 Pending
Array ( [id] => 20611570 [patent_doc_number] => 12587179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Ring oscillator-based true random number generator [patent_app_type] => utility [patent_app_number] => 18/768959 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768959 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768959
Ring oscillator-based true random number generator Jul 9, 2024 Issued
Array ( [id] => 20448954 [patent_doc_number] => 20260005680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => DIGITAL DUTY CYCLE CORRECTOR CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/756990 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756990
DIGITAL DUTY CYCLE CORRECTOR CIRCUIT Jun 26, 2024 Pending
Array ( [id] => 19662850 [patent_doc_number] => 20240429915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => ASYMMETRIC POWER MODULE [patent_app_type] => utility [patent_app_number] => 18/747785 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747785
ASYMMETRIC POWER MODULE Jun 18, 2024 Pending
Array ( [id] => 19867051 [patent_doc_number] => 20250105837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/739482 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739482
Semiconductor device Jun 10, 2024 Issued
Array ( [id] => 20389706 [patent_doc_number] => 12489444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Receiver circuit including differential buffer [patent_app_type] => utility [patent_app_number] => 18/739323 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739323
Receiver circuit including differential buffer Jun 10, 2024 Issued
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