
Ryan C. Jager
Examiner (ID: 2114, Phone: (571)272-7016 , Office: P/2842 )
| Most Active Art Unit | 2842 |
| Art Unit(s) | 2816, 2842, 2836 |
| Total Applications | 1406 |
| Issued Applications | 1239 |
| Pending Applications | 68 |
| Abandoned Applications | 123 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20827496
[patent_doc_number] => 12681056
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-07-14
[patent_title] => Voltage droop detection
[patent_app_type] => utility
[patent_app_number] => 18/925346
[patent_app_country] => US
[patent_app_date] => 2024-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1189
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925346
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/925346 | Voltage droop detection | Oct 23, 2024 | Issued |
Array
(
[id] => 20747160
[patent_doc_number] => 12647090
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Capacitive coupling isolation device and receiving circuit
[patent_app_type] => utility
[patent_app_number] => 18/922367
[patent_app_country] => US
[patent_app_date] => 2024-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1189
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922367
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/922367 | Capacitive coupling isolation device and receiving circuit | Oct 20, 2024 | Issued |
Array
(
[id] => 20312547
[patent_doc_number] => 20250330176
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-23
[patent_title] => CLOCK TRANSMISSION CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/918069
[patent_app_country] => US
[patent_app_date] => 2024-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13940
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18918069
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/918069 | CLOCK TRANSMISSION CIRCUIT | Oct 16, 2024 | Pending |
Array
(
[id] => 19994455
[patent_doc_number] => 20250132677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-24
[patent_title] => APPARATUS OF CONFIGURABLE PMIC WITH ARRAY OF MICRO INTEGRATED VOLTAGE REGULATION CELLS AND SHARED PROGRAMMABLE REFERENCES
[patent_app_type] => utility
[patent_app_number] => 18/919345
[patent_app_country] => US
[patent_app_date] => 2024-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6719
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919345
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/919345 | APPARATUS OF CONFIGURABLE PMIC WITH ARRAY OF MICRO INTEGRATED VOLTAGE REGULATION CELLS AND SHARED PROGRAMMABLE REFERENCES | Oct 16, 2024 | Pending |
Array
(
[id] => 20845421
[patent_doc_number] => 20260205005
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-07-16
[patent_title] => PULSE FORMATION DEVICE AND PULSE FORMATION METHOD USING THE SAME
[patent_app_type] => utility
[patent_app_number] => 19/137207
[patent_app_country] => US
[patent_app_date] => 2024-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1197
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19137207
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/137207 | PULSE FORMATION DEVICE AND PULSE FORMATION METHOD USING THE SAME | Oct 1, 2024 | Pending |
Array
(
[id] => 20448971
[patent_doc_number] => 20260005697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-01
[patent_title] => AVERAGING A DIGITAL PHASE LOCKED LOOP OUTPUT FREQUENCY TO CALCULATE A PRESET VALUE FOR USE IN THE EVENT OF A LINK LOSS
[patent_app_type] => utility
[patent_app_number] => 18/895490
[patent_app_country] => US
[patent_app_date] => 2024-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18895490
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/895490 | AVERAGING A DIGITAL PHASE LOCKED LOOP OUTPUT FREQUENCY TO CALCULATE A PRESET VALUE FOR USE IN THE EVENT OF A LINK LOSS | Sep 24, 2024 | Pending |
Array
(
[id] => 19867050
[patent_doc_number] => 20250105836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => GATE DRIVER CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/888754
[patent_app_country] => US
[patent_app_date] => 2024-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9965
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18888754
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/888754 | GATE DRIVER CIRCUIT | Sep 17, 2024 | Pending |
Array
(
[id] => 20637028
[patent_doc_number] => 12597917
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Power switch with normally on transistor
[patent_app_type] => utility
[patent_app_number] => 18/882850
[patent_app_country] => US
[patent_app_date] => 2024-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 0
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882850
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/882850 | Power switch with normally on transistor | Sep 11, 2024 | Issued |
Array
(
[id] => 19851454
[patent_doc_number] => 20250096805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-20
[patent_title] => CHARGE PUMP CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/828011
[patent_app_country] => US
[patent_app_date] => 2024-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6000
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828011
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/828011 | Charge pump circuit and phase-locked loop circuit | Sep 8, 2024 | Issued |
Array
(
[id] => 20382016
[patent_doc_number] => 20250364509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-27
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/828516
[patent_app_country] => US
[patent_app_date] => 2024-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1240
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828516
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/828516 | Semiconductor device | Sep 8, 2024 | Issued |
Array
(
[id] => 19865958
[patent_doc_number] => 20250104744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => SEMICONDUCTOR MODULE
[patent_app_type] => utility
[patent_app_number] => 18/827635
[patent_app_country] => US
[patent_app_date] => 2024-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11198
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 342
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18827635
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/827635 | SEMICONDUCTOR MODULE | Sep 5, 2024 | Pending |
Array
(
[id] => 19635365
[patent_doc_number] => 20240413814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => OSCILLATING SIGNAL GENERATING CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/810138
[patent_app_country] => US
[patent_app_date] => 2024-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13358
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810138
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/810138 | Oscillating signal generating circuit and a semiconductor apparatus using the same | Aug 19, 2024 | Issued |
Array
(
[id] => 20544988
[patent_doc_number] => 20260051881
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-02-19
[patent_title] => CLOCK PHASE TUNER EMPLOYING SET OF CONFIGURABLE SWITCHED-CURRENT UNIT CELLS
[patent_app_type] => utility
[patent_app_number] => 18/807335
[patent_app_country] => US
[patent_app_date] => 2024-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4489
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18807335
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/807335 | CLOCK PHASE TUNER EMPLOYING SET OF CONFIGURABLE SWITCHED-CURRENT UNIT CELLS | Aug 15, 2024 | Pending |
Array
(
[id] => 20852316
[patent_doc_number] => 12689359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-07-21
[patent_title] => Time delay calibrator and method
[patent_app_type] => utility
[patent_app_number] => 18/804674
[patent_app_country] => US
[patent_app_date] => 2024-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3600
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804674
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/804674 | TIME DELAY CALIBRATOR AND METHOD | Aug 13, 2024 | Pending |
Array
(
[id] => 20291888
[patent_doc_number] => 20250317131
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-09
[patent_title] => RECEIVER CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/805262
[patent_app_country] => US
[patent_app_date] => 2024-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9444
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805262
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/805262 | Receiver circuit, and semiconductor apparatus and semiconductor system using the same | Aug 13, 2024 | Issued |
Array
(
[id] => 20502330
[patent_doc_number] => 20260031793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-29
[patent_title] => GLITCH FILTER CIRCUITRY FOR DEVICE-TO-DEVICE COMMUNICATION SYSTEM INTERFACE
[patent_app_type] => utility
[patent_app_number] => 18/783174
[patent_app_country] => US
[patent_app_date] => 2024-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4530
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783174
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/783174 | GLITCH FILTER CIRCUITRY FOR DEVICE-TO-DEVICE COMMUNICATION SYSTEM INTERFACE | Jul 23, 2024 | Issued |
Array
(
[id] => 20251772
[patent_doc_number] => 20250300641
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => INPUT BUFFER CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/776866
[patent_app_country] => US
[patent_app_date] => 2024-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1130
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776866
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/776866 | INPUT BUFFER CIRCUIT | Jul 17, 2024 | Pending |
Array
(
[id] => 19560761
[patent_doc_number] => 20240372553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => METHODS AND APPARATUS TO DYNAMICALLY CORRECT TIME KEEPING ERRORS
[patent_app_type] => utility
[patent_app_number] => 18/773777
[patent_app_country] => US
[patent_app_date] => 2024-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13708
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773777
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/773777 | Methods and apparatus to dynamically correct time keeping errors | Jul 15, 2024 | Issued |
Array
(
[id] => 19774020
[patent_doc_number] => 20250055446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-13
[patent_title] => QUADRATURE PHASE SHIFTED CLOCK GENERATION WITH DUTY CYCLE CORRECTION
[patent_app_type] => utility
[patent_app_number] => 18/771327
[patent_app_country] => US
[patent_app_date] => 2024-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5354
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771327
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/771327 | Quadrature phase shifted clock generation with duty cycle correction | Jul 11, 2024 | Issued |
Array
(
[id] => 20611570
[patent_doc_number] => 12587179
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-24
[patent_title] => Ring oscillator-based true random number generator
[patent_app_type] => utility
[patent_app_number] => 18/768959
[patent_app_country] => US
[patent_app_date] => 2024-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 0
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768959
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/768959 | Ring oscillator-based true random number generator | Jul 9, 2024 | Issued |