Search

Ryan C. Jager

Examiner (ID: 7849, Phone: (571)272-7016 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2842, 2816
Total Applications
1380
Issued Applications
1226
Pending Applications
58
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12129824 [patent_doc_number] => 20180013410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'Window Function Processing Module' [patent_app_type] => utility [patent_app_number] => 15/696195 [patent_app_country] => US [patent_app_date] => 2017-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5316 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15696195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/696195
Window function processing module Sep 5, 2017 Issued
Array ( [id] => 16440296 [patent_doc_number] => 20200357623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => HIGH-VOLTAGE POWER SUPPLY DEVICE [patent_app_type] => utility [patent_app_number] => 16/640544 [patent_app_country] => US [patent_app_date] => 2017-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16640544 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/640544
High-voltage power supply device Sep 3, 2017 Issued
Array ( [id] => 12060476 [patent_doc_number] => 20170336820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'APPARATUSES AND RELATED METHODS FOR STAGGERING POWER-UP OF A STACK OF SEMICONDUCTOR DIES' [patent_app_type] => utility [patent_app_number] => 15/671960 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671960 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/671960
Apparatuses and related methods for staggering power-up of a stack of semiconductor dies Aug 7, 2017 Issued
Array ( [id] => 12055120 [patent_doc_number] => 20170331464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT, LATCH CIRCUIT, AND FLIP-FLOP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/665070 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6911 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/665070
Semiconductor integrated circuit, latch circuit, and flip-flop circuit Jul 30, 2017 Issued
Array ( [id] => 12597927 [patent_doc_number] => 20180091139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => OUTPUT STAGE BUFFER CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/662442 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662442 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/662442
Output stage buffer circuit Jul 27, 2017 Issued
Array ( [id] => 12163189 [patent_doc_number] => 20180034455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'TRANSMITTER AND TRANSMISSION/RECEPTION SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/659772 [patent_app_country] => US [patent_app_date] => 2017-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6318 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15659772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/659772
Transmitter and transmission/reception system Jul 25, 2017 Issued
Array ( [id] => 12695317 [patent_doc_number] => 20180123605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => DIGITAL SYNTHESIZER, COMMUNICATION UNIT AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/660649 [patent_app_country] => US [patent_app_date] => 2017-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15660649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/660649
Digital synthesizer, communication unit and method therefor Jul 25, 2017 Issued
Array ( [id] => 12852010 [patent_doc_number] => 20180175843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => ASYNCHRONOUS CLOCK SIGNAL GENERATOR AND SEMICONDUCTOR DEVICE FOR CORRECTING MULTI-PHASE SIGNALS USING ASYNCHRONOUS CLOCK SIGNAL [patent_app_type] => utility [patent_app_number] => 15/658272 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/658272
Asynchronous clock signal generator and semiconductor device for correcting multi-phase signals using asynchronous clock signal Jul 23, 2017 Issued
Array ( [id] => 12163202 [patent_doc_number] => 20180034469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'FREQUENCY DIVISION CORRECTION CIRCUIT, RECEPTION CIRCUIT, AND INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/656716 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656716 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/656716
Frequency division correction circuit, reception circuit, and integrated circuit Jul 20, 2017 Issued
Array ( [id] => 14617943 [patent_doc_number] => 10361684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Duty cycle detection [patent_app_type] => utility [patent_app_number] => 15/654595 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4554 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654595 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/654595
Duty cycle detection Jul 18, 2017 Issued
Array ( [id] => 14559655 [patent_doc_number] => 10348303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Differential level shift circuit [patent_app_type] => utility [patent_app_number] => 15/652471 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652471
Differential level shift circuit Jul 17, 2017 Issued
Array ( [id] => 12027572 [patent_doc_number] => 20170317671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/651127 [patent_app_country] => US [patent_app_date] => 2017-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3858 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/651127
Semiconductor device performing boot-up operation Jul 16, 2017 Issued
Array ( [id] => 13833697 [patent_doc_number] => 20190020333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => DOUBLE COMPRESSION AVOIDANCE [patent_app_type] => utility [patent_app_number] => 15/649771 [patent_app_country] => US [patent_app_date] => 2017-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649771 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649771
Double compression avoidance Jul 13, 2017 Issued
Array ( [id] => 13977953 [patent_doc_number] => 10218349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => IGBT having improved clamp arrangement [patent_app_type] => utility [patent_app_number] => 15/641877 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1680 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641877
IGBT having improved clamp arrangement Jul 4, 2017 Issued
Array ( [id] => 14765731 [patent_doc_number] => 10394260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Gate boosting circuit and method for an integrated power stage [patent_app_type] => utility [patent_app_number] => 15/633527 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3707 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/633527
Gate boosting circuit and method for an integrated power stage Jun 25, 2017 Issued
Array ( [id] => 12055139 [patent_doc_number] => 20170331483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'Wide Range Frequency Synthesizer with Quadrature Generation and Spur Cancellation' [patent_app_type] => utility [patent_app_number] => 15/605932 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7089 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605932 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605932
Wide range frequency synthesizer with quadrature generation and spur cancellation May 24, 2017 Issued
Array ( [id] => 14368345 [patent_doc_number] => 10305494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Delay locked loop including a delay code generator [patent_app_type] => utility [patent_app_number] => 15/599191 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 9280 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599191
Delay locked loop including a delay code generator May 17, 2017 Issued
Array ( [id] => 12761494 [patent_doc_number] => 20180145666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => MULTIPLEXER BASED FREQUENCY EXTENDER [patent_app_type] => utility [patent_app_number] => 15/598003 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598003 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598003
Multiplexer based frequency extender May 16, 2017 Issued
Array ( [id] => 14493417 [patent_doc_number] => 10333513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Signal multiplexer [patent_app_type] => utility [patent_app_number] => 15/596200 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10027 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596200 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596200
Signal multiplexer May 15, 2017 Issued
Array ( [id] => 14559607 [patent_doc_number] => 10348279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Skew control [patent_app_type] => utility [patent_app_number] => 15/593079 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 10108 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593079 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/593079
Skew control May 10, 2017 Issued
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