Search

Ryan C. Jager

Examiner (ID: 2114, Phone: (571)272-7016 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2816, 2842, 2836
Total Applications
1406
Issued Applications
1239
Pending Applications
68
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20704565 [patent_doc_number] => 12627286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Digital duty cycle corrector circuit [patent_app_type] => utility [patent_app_number] => 18/756990 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756990
Digital duty cycle corrector circuit Jun 26, 2024 Issued
Array ( [id] => 19662850 [patent_doc_number] => 20240429915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => ASYMMETRIC POWER MODULE [patent_app_type] => utility [patent_app_number] => 18/747785 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747785
ASYMMETRIC POWER MODULE Jun 18, 2024 Pending
Array ( [id] => 20389706 [patent_doc_number] => 12489444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Receiver circuit including differential buffer [patent_app_type] => utility [patent_app_number] => 18/739323 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739323
Receiver circuit including differential buffer Jun 10, 2024 Issued
Array ( [id] => 19867051 [patent_doc_number] => 20250105837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/739482 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739482
Semiconductor device Jun 10, 2024 Issued
Array ( [id] => 20733453 [patent_doc_number] => 12640715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Demodulation circuit and digital isolator [patent_app_type] => utility [patent_app_number] => 18/735140 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735140
Demodulation circuit and digital isolator Jun 4, 2024 Issued
Array ( [id] => 20830001 [patent_doc_number] => 12683588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Cross-coupled latch charge pump as well as a method of operating such a cross-coupled latch charge pump [patent_app_type] => utility [patent_app_number] => 18/679876 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679876
Cross-coupled latch charge pump as well as a method of operating such a cross-coupled latch charge pump May 30, 2024 Issued
Array ( [id] => 20690823 [patent_doc_number] => 12620985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Low power consumption power-on reset system [patent_app_type] => utility [patent_app_number] => 18/671940 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671940
Low power consumption power-on reset system May 21, 2024 Issued
Array ( [id] => 20215874 [patent_doc_number] => 12412528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 18/668968 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6800 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668968
Display device May 19, 2024 Issued
Array ( [id] => 20045664 [patent_doc_number] => 20250183886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => MULTI-RANGE TEMPERATURE COMPENSATION FOR PROGRAMMABLE CIRCUIT ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/667321 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667321
MULTI-RANGE TEMPERATURE COMPENSATION FOR PROGRAMMABLE CIRCUIT ELEMENTS May 16, 2024 Pending
Array ( [id] => 19821891 [patent_doc_number] => 20250080098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => ON-RESISTANCE ENHANCEMENT FOR POWER CONVERTER [patent_app_type] => utility [patent_app_number] => 18/664044 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664044
ON-RESISTANCE ENHANCEMENT FOR POWER CONVERTER May 13, 2024 Pending
Array ( [id] => 19419775 [patent_doc_number] => 20240295898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MULTI-CHIPLET CLOCK DELAY COMPENSATION [patent_app_type] => utility [patent_app_number] => 18/663864 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663864
MULTI-CHIPLET CLOCK DELAY COMPENSATION May 13, 2024 Pending
Array ( [id] => 20747176 [patent_doc_number] => 12647106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Storage device having latching units serially connected for in-memory arithmetic operations [patent_app_type] => utility [patent_app_number] => 18/663560 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 43 [patent_no_of_words] => 6007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663560
Storage device having latching units serially connected for in-memory arithmetic operations May 13, 2024 Issued
Array ( [id] => 19590722 [patent_doc_number] => 20240388279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => CLOCK OUTPUT DEVICE AND CLOCK DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 18/659520 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659520
Clock output device and clock detection method May 8, 2024 Issued
Array ( [id] => 19880204 [patent_doc_number] => 20250112461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => DYNAMIC SELECTION OF POWER ROUTES IN CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/640206 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640206 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640206
DYNAMIC SELECTION OF POWER ROUTES IN CIRCUITS Apr 18, 2024 Pending
Array ( [id] => 20312551 [patent_doc_number] => 20250330180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => CLOCK SYNC INPUT DROPOUT PROTECTION [patent_app_type] => utility [patent_app_number] => 18/637661 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637661 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637661
CLOCK SYNC INPUT DROPOUT PROTECTION Apr 16, 2024 Pending
Array ( [id] => 20469923 [patent_doc_number] => 12525966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Digital phase interpolator [patent_app_type] => utility [patent_app_number] => 18/636983 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636983
Digital phase interpolator Apr 15, 2024 Issued
Array ( [id] => 19350040 [patent_doc_number] => 20240259004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => DRIVING BUFFER WITH CONFIGURABLE SLEW RATE FOR DATA TRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/632381 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632381
Driving buffer with configurable slew rate for data transmission Apr 10, 2024 Issued
Array ( [id] => 19350036 [patent_doc_number] => 20240259000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => CIRCUIT BOARD STRUCTURE, INFORMATION PROCESSING METHOD AND APPARATUS, AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 18/633292 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633292 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633292
Circuit board structure, information processing method and apparatus, and communication device Apr 10, 2024 Issued
Array ( [id] => 20581762 [patent_doc_number] => 12574020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Dynamic eye opening monitor [patent_app_type] => utility [patent_app_number] => 18/631885 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631885 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631885
Dynamic eye opening monitor Apr 9, 2024 Issued
Array ( [id] => 19590720 [patent_doc_number] => 20240388277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => ELECTRONIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/632231 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632231 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632231
ELECTRONIC CIRCUIT Apr 9, 2024 Pending
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