Search

Ryan C. Rufo

Examiner (ID: 356, Phone: (571)272-4604 , Office: P/3722 )

Most Active Art Unit
3722
Art Unit(s)
3722, 3724
Total Applications
790
Issued Applications
421
Pending Applications
104
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19972219 [patent_doc_number] => 12340837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Recognition system and SRAM cell thereof [patent_app_type] => utility [patent_app_number] => 18/629735 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629735 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629735
Recognition system and SRAM cell thereof Apr 7, 2024 Issued
Array ( [id] => 20265703 [patent_doc_number] => 12436694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Configurable memory die capacitance [patent_app_type] => utility [patent_app_number] => 18/604203 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604203
Configurable memory die capacitance Mar 12, 2024 Issued
Array ( [id] => 20181034 [patent_doc_number] => 20250264992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => SENSING WITHIN AN EMBEDDED DYNAMIC RANDOM ACCESS MEMORIES (DRAMS) HAVING REFERENCE CELLS [patent_app_type] => utility [patent_app_number] => 18/444816 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444816 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444816
SENSING WITHIN AN EMBEDDED DYNAMIC RANDOM ACCESS MEMORIES (DRAMS) HAVING REFERENCE CELLS Feb 18, 2024 Pending
Array ( [id] => 19391278 [patent_doc_number] => 20240281148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => DYNAMIC ERASE VOLTAGE STEP [patent_app_type] => utility [patent_app_number] => 18/443584 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443584
DYNAMIC ERASE VOLTAGE STEP Feb 15, 2024 Pending
Array ( [id] => 19687747 [patent_doc_number] => 20250006292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/440619 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440619
STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES Feb 12, 2024 Pending
Array ( [id] => 19986735 [patent_doc_number] => 20250124957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => MEMORY DEVICE INCLUDING PIPE LATCH [patent_app_type] => utility [patent_app_number] => 18/436021 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436021
MEMORY DEVICE INCLUDING PIPE LATCH Feb 7, 2024 Pending
Array ( [id] => 20153143 [patent_doc_number] => 20250252981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE, COMPUTING CIRCUIT AND COMPUTING METHOD [patent_app_type] => utility [patent_app_number] => 18/435006 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435006 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435006
THREE-DIMENSIONAL MEMORY DEVICE, COMPUTING CIRCUIT AND COMPUTING METHOD Feb 6, 2024 Pending
Array ( [id] => 19205854 [patent_doc_number] => 20240177753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => APPARATUS AND METHOD FOR HARDWARE METERING USING MEMORY-TYPE CAMOUFLAGED CELL [patent_app_type] => utility [patent_app_number] => 18/432390 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432390 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432390
Apparatus and method for hardware metering using memory-type camouflaged cell Feb 4, 2024 Issued
Array ( [id] => 19363952 [patent_doc_number] => 20240265986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => CIRCUIT AND METHOD FOR CARRYING OUT A VECTOR OPERATION [patent_app_type] => utility [patent_app_number] => 18/430945 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430945
CIRCUIT AND METHOD FOR CARRYING OUT A VECTOR OPERATION Feb 1, 2024 Pending
Array ( [id] => 20153159 [patent_doc_number] => 20250252997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => LEAKAGE COMPENSATION CIRCUIT FOR CONTENT ADDRESSABLE MEMORY (CAM) CELL [patent_app_type] => utility [patent_app_number] => 18/430301 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430301
LEAKAGE COMPENSATION CIRCUIT FOR CONTENT ADDRESSABLE MEMORY (CAM) CELL Jan 31, 2024 Pending
Array ( [id] => 20139188 [patent_doc_number] => 20250246232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => HYBRID BOOSTING FOR MEMORY WRITE ASSIST [patent_app_type] => utility [patent_app_number] => 18/428482 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428482
HYBRID BOOSTING FOR MEMORY WRITE ASSIST Jan 30, 2024 Pending
Array ( [id] => 19712382 [patent_doc_number] => 20250022524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => MEMORY DEVICE AND METHOD FOR CALIBRATING IMPEDANCE THEREOF [patent_app_type] => utility [patent_app_number] => 18/428418 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428418
MEMORY DEVICE AND METHOD FOR CALIBRATING IMPEDANCE THEREOF Jan 30, 2024 Pending
Array ( [id] => 20096076 [patent_doc_number] => 20250226012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => CIRCUIT AND METHOD FOR POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/426899 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426899 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426899
CIRCUIT AND METHOD FOR POWER MANAGEMENT Jan 29, 2024 Pending
Array ( [id] => 20139184 [patent_doc_number] => 20250246228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/422185 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422185 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422185
MEMORY DEVICE Jan 24, 2024 Pending
Array ( [id] => 19788259 [patent_doc_number] => 20250061938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MEMORY DEVICE INCLUDING SENSE AMPLIFIER AND METHOD OF STORING DATA THEREOF [patent_app_type] => utility [patent_app_number] => 18/421152 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421152
Memory device including sense amplifier and method of storing data thereof Jan 23, 2024 Issued
Array ( [id] => 20718067 [patent_doc_number] => 12633322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Current detector and information processor [patent_app_type] => utility [patent_app_number] => 18/421801 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 2295 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421801
Current detector and information processor Jan 23, 2024 Issued
Array ( [id] => 20624779 [patent_doc_number] => 12592291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Non-volatile memory with in-place error updating and correction [patent_app_type] => utility [patent_app_number] => 18/419205 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 17822 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419205
Non-volatile memory with in-place error updating and correction Jan 21, 2024 Issued
Array ( [id] => 19757786 [patent_doc_number] => 20250046351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => POWER EFFICIENT UNMATCHED DATA PATH ARCHITECTURE FOR NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/414004 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414004 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414004
Power efficient unmatched data path architecture for non-volatile memory Jan 15, 2024 Issued
Array ( [id] => 20102868 [patent_doc_number] => 20250232804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY DEVICES WITH RC TRACKING AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/410739 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410739
MEMORY DEVICES WITH RC TRACKING AND METHODS FOR OPERATING THE SAME Jan 10, 2024 Pending
Array ( [id] => 20564841 [patent_doc_number] => 12567455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Reference potential generating circuit and control method thereof [patent_app_type] => utility [patent_app_number] => 18/407830 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407830 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/407830
Reference potential generating circuit and control method thereof Jan 8, 2024 Issued
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