Search

Ryan C. Rufo

Examiner (ID: 356, Phone: (571)272-4604 , Office: P/3722 )

Most Active Art Unit
3722
Art Unit(s)
3722, 3724
Total Applications
790
Issued Applications
421
Pending Applications
104
Abandoned Applications
276

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19145981 [patent_doc_number] => 20240144996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => FAST DIRECT LOOK AHEAD READ MODE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/356774 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356774
Fast direct look ahead read mode in a memory device Jul 20, 2023 Issued
Array ( [id] => 19406891 [patent_doc_number] => 20240290402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => INTERMEDIATE RE-VERIFY FOR ACHIEVING TIGHTER THRESHOLD VOLTAGE DISTRIBUTIONS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/223782 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223782
Intermediate re-verify for achieving tighter threshold voltage distributions in a memory device Jul 18, 2023 Issued
Array ( [id] => 19205872 [patent_doc_number] => 20240177771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SELF-SELECTING MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/334790 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334790
Self-selecting memory device, memory system having the same, and operating method thereof Jun 13, 2023 Issued
Array ( [id] => 19633014 [patent_doc_number] => 20240411463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/331612 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331612
QUEUED CURRENT LEVEL ADJUSTMENT IN A FLASH MEMORY SYSTEM Jun 7, 2023 Abandoned
Array ( [id] => 20375065 [patent_doc_number] => 12482507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory device configured to generate read current based on size of memory cell and value of read current actually applied to memory cell [patent_app_type] => utility [patent_app_number] => 18/329215 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 8498 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329215
Memory device configured to generate read current based on size of memory cell and value of read current actually applied to memory cell Jun 4, 2023 Issued
Array ( [id] => 18652812 [patent_doc_number] => 20230298652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/200871 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200871 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200871
Memory device having 2-transistor vertical memory cell and shield structures May 22, 2023 Issued
Array ( [id] => 19980030 [patent_doc_number] => 12347516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Random access memory and sense-amplifying compensation circuit thereof [patent_app_type] => utility [patent_app_number] => 18/197106 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197106
Random access memory and sense-amplifying compensation circuit thereof May 14, 2023 Issued
Array ( [id] => 18659746 [patent_doc_number] => 20230305753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => MEMORY SYSTEM AND SHIFT REGISTER MEMORY [patent_app_type] => utility [patent_app_number] => 18/309038 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309038 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309038
Memory system and shift register memory Apr 27, 2023 Issued
Array ( [id] => 18570248 [patent_doc_number] => 20230260585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => POWER CIRCUIT AND METHOD FOR PROVIDING POWER TO ELECTRONIC FUSE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/306221 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306221 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306221
Electronic fuse circuit and method for electronic fuse circuit Apr 23, 2023 Issued
Array ( [id] => 19347183 [patent_doc_number] => 20240256146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REDUNDANCY FOR AN ARRAY OF NON-VOLATILE MEMORY CELLS USING TAG REGISTERS [patent_app_type] => utility [patent_app_number] => 18/134928 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134928
Redundancy for an array of non-volatile memory cells using tag registers Apr 13, 2023 Issued
Array ( [id] => 19347183 [patent_doc_number] => 20240256146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REDUNDANCY FOR AN ARRAY OF NON-VOLATILE MEMORY CELLS USING TAG REGISTERS [patent_app_type] => utility [patent_app_number] => 18/134928 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134928
Redundancy for an array of non-volatile memory cells using tag registers Apr 13, 2023 Issued
Array ( [id] => 19347183 [patent_doc_number] => 20240256146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REDUNDANCY FOR AN ARRAY OF NON-VOLATILE MEMORY CELLS USING TAG REGISTERS [patent_app_type] => utility [patent_app_number] => 18/134928 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134928
Redundancy for an array of non-volatile memory cells using tag registers Apr 13, 2023 Issued
Array ( [id] => 19347183 [patent_doc_number] => 20240256146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REDUNDANCY FOR AN ARRAY OF NON-VOLATILE MEMORY CELLS USING TAG REGISTERS [patent_app_type] => utility [patent_app_number] => 18/134928 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134928
Redundancy for an array of non-volatile memory cells using tag registers Apr 13, 2023 Issued
Array ( [id] => 18553931 [patent_doc_number] => 20230251943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => ROW REPAIR AND ACCURACY IMPROVEMENTS IN ANALOG COMPUTE-IN-MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/298906 [patent_app_country] => US [patent_app_date] => 2023-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18298906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/298906
ROW REPAIR AND ACCURACY IMPROVEMENTS IN ANALOG COMPUTE-IN-MEMORY ARCHITECTURES Apr 10, 2023 Pending
Array ( [id] => 18696064 [patent_doc_number] => 20230326495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM HAVING INDEPENDENT DATA INPUT/OUTPUT PERIOD, AND OPERATING METHOD OF THE SEMICONDUCTOR SYSTEM [patent_app_type] => utility [patent_app_number] => 18/297307 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297307 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297307
Semiconductor apparatus and semiconductor system having independent data input/output period, and operating method of the semiconductor system Apr 6, 2023 Issued
Array ( [id] => 18661066 [patent_doc_number] => 20230307079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => MEMORY SYSTEM WITH ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 18/295445 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295445
Memory system with error detection Apr 3, 2023 Issued
Array ( [id] => 20317150 [patent_doc_number] => 12455700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Increased shift frequency for multi-chip-module scan [patent_app_type] => utility [patent_app_number] => 18/194390 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194390 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194390
Increased shift frequency for multi-chip-module scan Mar 30, 2023 Issued
Array ( [id] => 18555041 [patent_doc_number] => 20230253057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE, AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/192367 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192367
Nonvolatile memory device, storage device including nonvolatile memory device, and operating method of nonvolatile memory device Mar 28, 2023 Issued
Array ( [id] => 19084177 [patent_doc_number] => 20240110978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SEMICONDUCTOR CHIP AND SEQUENCE CHECKING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/190144 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190144 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190144
Semiconductor chip and sequence checking circuit Mar 26, 2023 Issued
Array ( [id] => 18661023 [patent_doc_number] => 20230307036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => Storage and Accessing Methods for Parameters in Streaming AI Accelerator Chip [patent_app_type] => utility [patent_app_number] => 18/184686 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184686
Storage and accessing methods for parameters in streaming AI accelerator chip Mar 15, 2023 Issued
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