Search

Ryan H. Ellis

Examiner (ID: 365)

Most Active Art Unit
3745
Art Unit(s)
3745
Total Applications
361
Issued Applications
222
Pending Applications
6
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1423337 [patent_doc_number] => 06522187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'CMOS switch with linearized gate capacitance' [patent_app_type] => B1 [patent_app_number] => 09/804348 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2560 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522187.pdf [firstpage_image] =>[orig_patent_app_number] => 09804348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804348
CMOS switch with linearized gate capacitance Mar 11, 2001 Issued
Array ( [id] => 1530066 [patent_doc_number] => 06480058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Differential pair with controlled degeneration' [patent_app_type] => B2 [patent_app_number] => 09/790418 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4405 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480058.pdf [firstpage_image] =>[orig_patent_app_number] => 09790418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790418
Differential pair with controlled degeneration Feb 21, 2001 Issued
Array ( [id] => 1476849 [patent_doc_number] => 06388478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Configurable clock generator' [patent_app_type] => B1 [patent_app_number] => 09/782482 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3708 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388478.pdf [firstpage_image] =>[orig_patent_app_number] => 09782482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/782482
Configurable clock generator Feb 12, 2001 Issued
Array ( [id] => 1583617 [patent_doc_number] => 06424180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Digital phase shift amplification and detection system and method' [patent_app_type] => B1 [patent_app_number] => 09/780663 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11225 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424180.pdf [firstpage_image] =>[orig_patent_app_number] => 09780663 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780663
Digital phase shift amplification and detection system and method Feb 7, 2001 Issued
Array ( [id] => 6933577 [patent_doc_number] => 20010054921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Semiconductor integrated circuit and method for initializing the same' [patent_app_type] => new [patent_app_number] => 09/769534 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3376 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054921.pdf [firstpage_image] =>[orig_patent_app_number] => 09769534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769534
Power-on reset circuit/method for initializing an integrated circuit Jan 25, 2001 Issued
Array ( [id] => 1548272 [patent_doc_number] => 06445225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-03 [patent_title] => 'Line driver with variable power' [patent_app_type] => B2 [patent_app_number] => 09/769493 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445225.pdf [firstpage_image] =>[orig_patent_app_number] => 09769493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769493
Line driver with variable power Jan 25, 2001 Issued
Array ( [id] => 6876200 [patent_doc_number] => 20010006353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Electronic circuit' [patent_app_type] => new-utility [patent_app_number] => 09/739636 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2434 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006353.pdf [firstpage_image] =>[orig_patent_app_number] => 09739636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739636
Amplifier circuit and preconditioning circuit for use in amplifier circuit Dec 19, 2000 Issued
Array ( [id] => 1576901 [patent_doc_number] => 06469556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Pulse-controlled analog flip-flop' [patent_app_type] => B2 [patent_app_number] => 09/735407 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469556.pdf [firstpage_image] =>[orig_patent_app_number] => 09735407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735407
Pulse-controlled analog flip-flop Dec 11, 2000 Issued
Array ( [id] => 1603438 [patent_doc_number] => 06433620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Silicon-on-insulator CMOS circuit' [patent_app_type] => B1 [patent_app_number] => 09/716260 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6334 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433620.pdf [firstpage_image] =>[orig_patent_app_number] => 09716260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/716260
Silicon-on-insulator CMOS circuit Nov 20, 2000 Issued
09/715949 Charge pump mode transition control Nov 16, 2000 Abandoned
Array ( [id] => 1571672 [patent_doc_number] => 06498524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Input/output data synchronizing device' [patent_app_type] => B1 [patent_app_number] => 09/706731 [patent_app_country] => US [patent_app_date] => 2000-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 88 [patent_figures_cnt] => 100 [patent_no_of_words] => 31080 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498524.pdf [firstpage_image] =>[orig_patent_app_number] => 09706731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706731
Input/output data synchronizing device Nov 6, 2000 Issued
Array ( [id] => 1502901 [patent_doc_number] => 06486730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Voltage down pump and method of operation' [patent_app_type] => B1 [patent_app_number] => 09/695721 [patent_app_country] => US [patent_app_date] => 2000-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3152 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486730.pdf [firstpage_image] =>[orig_patent_app_number] => 09695721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/695721
Voltage down pump and method of operation Oct 22, 2000 Issued
Array ( [id] => 1525185 [patent_doc_number] => 06353357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Controlling transistor threshold potentials using substrate potentials' [patent_app_type] => B1 [patent_app_number] => 09/693769 [patent_app_country] => US [patent_app_date] => 2000-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3114 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353357.pdf [firstpage_image] =>[orig_patent_app_number] => 09693769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/693769
Controlling transistor threshold potentials using substrate potentials Oct 19, 2000 Issued
Array ( [id] => 1292585 [patent_doc_number] => RE038250 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Bandgap reference circuit' [patent_app_type] => E1 [patent_app_number] => 09/684192 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038250.pdf [firstpage_image] =>[orig_patent_app_number] => 09684192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684192
Bandgap reference circuit Oct 5, 2000 Issued
Array ( [id] => 1460330 [patent_doc_number] => 06426658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Buffers with reduced voltage input/output signals' [patent_app_type] => B1 [patent_app_number] => 09/676864 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3900 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426658.pdf [firstpage_image] =>[orig_patent_app_number] => 09676864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676864
Buffers with reduced voltage input/output signals Sep 28, 2000 Issued
Array ( [id] => 1177158 [patent_doc_number] => 06750698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Cascade circuits utilizing normally-off junction field effect transistors for low on-resistance and low voltage applications' [patent_app_type] => B1 [patent_app_number] => 09/676370 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2364 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750698.pdf [firstpage_image] =>[orig_patent_app_number] => 09676370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676370
Cascade circuits utilizing normally-off junction field effect transistors for low on-resistance and low voltage applications Sep 28, 2000 Issued
Array ( [id] => 7643319 [patent_doc_number] => 06429723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Integrated circuit with charge pump and method' [patent_app_type] => B1 [patent_app_number] => 09/658776 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 5543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429723.pdf [firstpage_image] =>[orig_patent_app_number] => 09658776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658776
Integrated circuit with charge pump and method Sep 10, 2000 Issued
Array ( [id] => 1530047 [patent_doc_number] => 06480050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Level shifter with no quiescent DC current flow' [patent_app_type] => B1 [patent_app_number] => 09/658048 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2011 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480050.pdf [firstpage_image] =>[orig_patent_app_number] => 09658048 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658048
Level shifter with no quiescent DC current flow Sep 7, 2000 Issued
Array ( [id] => 1545040 [patent_doc_number] => 06373331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method and apparatus for reducing transistor amplifier hysteresis' [patent_app_type] => B1 [patent_app_number] => 09/658668 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6082 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373331.pdf [firstpage_image] =>[orig_patent_app_number] => 09658668 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658668
Method and apparatus for reducing transistor amplifier hysteresis Sep 7, 2000 Issued
Array ( [id] => 1603374 [patent_doc_number] => 06433556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Circuit for generating a ramp signal between two temperature points of operation' [patent_app_type] => B1 [patent_app_number] => 09/655892 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433556.pdf [firstpage_image] =>[orig_patent_app_number] => 09655892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655892
Circuit for generating a ramp signal between two temperature points of operation Sep 5, 2000 Issued
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