Search

Ryan H. Ellis

Examiner (ID: 365)

Most Active Art Unit
3745
Art Unit(s)
3745
Total Applications
361
Issued Applications
222
Pending Applications
6
Abandoned Applications
135

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4364386 [patent_doc_number] => 06175255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Line driver circuit for low voltage and low power applications' [patent_app_type] => 1 [patent_app_number] => 9/198129 [patent_app_country] => US [patent_app_date] => 1998-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6013 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175255.pdf [firstpage_image] =>[orig_patent_app_number] => 198129 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/198129
Line driver circuit for low voltage and low power applications Nov 22, 1998 Issued
Array ( [id] => 4424447 [patent_doc_number] => 06177829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Device for improving the switching efficiency of an integrated circuit charge pump' [patent_app_type] => 1 [patent_app_number] => 9/196335 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2457 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177829.pdf [firstpage_image] =>[orig_patent_app_number] => 196335 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196335
Device for improving the switching efficiency of an integrated circuit charge pump Nov 18, 1998 Issued
Array ( [id] => 4191970 [patent_doc_number] => 06150870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Adjustable substrate voltage applying circuit of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/195202 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2805 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150870.pdf [firstpage_image] =>[orig_patent_app_number] => 195202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195202
Adjustable substrate voltage applying circuit of a semiconductor device Nov 17, 1998 Issued
Array ( [id] => 4412434 [patent_doc_number] => 06271714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Substrate voltage generator for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/192275 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 3455 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271714.pdf [firstpage_image] =>[orig_patent_app_number] => 192275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192275
Substrate voltage generator for semiconductor device Nov 15, 1998 Issued
Array ( [id] => 4343129 [patent_doc_number] => 06333669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Voltage converting circuit allowing control of current drivability in accordance with operational frequency' [patent_app_type] => 1 [patent_app_number] => 9/191122 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4636 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333669.pdf [firstpage_image] =>[orig_patent_app_number] => 191122 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191122
Voltage converting circuit allowing control of current drivability in accordance with operational frequency Nov 12, 1998 Issued
Array ( [id] => 7610805 [patent_doc_number] => 06842053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Reduced charge injection in current switch' [patent_app_type] => utility [patent_app_number] => 09/188241 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3513 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842053.pdf [firstpage_image] =>[orig_patent_app_number] => 09188241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188241
Reduced charge injection in current switch Nov 8, 1998 Issued
Array ( [id] => 4303882 [patent_doc_number] => 06184745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Reference voltage generating circuit' [patent_app_type] => 1 [patent_app_number] => 9/178476 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2703 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184745.pdf [firstpage_image] =>[orig_patent_app_number] => 178476 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178476
Reference voltage generating circuit Oct 25, 1998 Issued
Array ( [id] => 4197310 [patent_doc_number] => 06154065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Sense amplifier circuit' [patent_app_type] => 1 [patent_app_number] => 9/174370 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 4206 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154065.pdf [firstpage_image] =>[orig_patent_app_number] => 174370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174370
Sense amplifier circuit Oct 14, 1998 Issued
Array ( [id] => 1383267 [patent_doc_number] => 06563373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Filter circuit utilizing a plurality of sampling and holding circuits' [patent_app_type] => B1 [patent_app_number] => 09/165301 [patent_app_country] => US [patent_app_date] => 1998-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 5672 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563373.pdf [firstpage_image] =>[orig_patent_app_number] => 09165301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165301
Filter circuit utilizing a plurality of sampling and holding circuits Oct 1, 1998 Issued
Array ( [id] => 4415914 [patent_doc_number] => 06265904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Digital phase shift amplification and detection system and method' [patent_app_type] => 1 [patent_app_number] => 9/165415 [patent_app_country] => US [patent_app_date] => 1998-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11032 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265904.pdf [firstpage_image] =>[orig_patent_app_number] => 165415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165415
Digital phase shift amplification and detection system and method Oct 1, 1998 Issued
Array ( [id] => 4245962 [patent_doc_number] => 06081152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Output buffer with protective limit of voltage across terminals of devices within the output buffer' [patent_app_type] => 1 [patent_app_number] => 9/165489 [patent_app_country] => US [patent_app_date] => 1998-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5532 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081152.pdf [firstpage_image] =>[orig_patent_app_number] => 165489 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165489
Output buffer with protective limit of voltage across terminals of devices within the output buffer Oct 1, 1998 Issued
Array ( [id] => 4088975 [patent_doc_number] => 06054888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Level shifter with protective limit of voltage across terminals of devices within the level shifter' [patent_app_type] => 1 [patent_app_number] => 9/165911 [patent_app_country] => US [patent_app_date] => 1998-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9180 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 810 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054888.pdf [firstpage_image] =>[orig_patent_app_number] => 165911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165911
Level shifter with protective limit of voltage across terminals of devices within the level shifter Oct 1, 1998 Issued
Array ( [id] => 4299970 [patent_doc_number] => 06236257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method and apparatus for reducing using feed forward compensation' [patent_app_type] => 1 [patent_app_number] => 9/164867 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2305 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236257.pdf [firstpage_image] =>[orig_patent_app_number] => 164867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164867
Method and apparatus for reducing using feed forward compensation Sep 30, 1998 Issued
Array ( [id] => 1581048 [patent_doc_number] => 06448846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-10 [patent_title] => 'Controlled phase-canceling circuits/systems' [patent_app_type] => B2 [patent_app_number] => 09/164875 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3247 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448846.pdf [firstpage_image] =>[orig_patent_app_number] => 09164875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164875
Controlled phase-canceling circuits/systems Sep 30, 1998 Issued
Array ( [id] => 4302633 [patent_doc_number] => 06181173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Power-on reset circuit' [patent_app_type] => 1 [patent_app_number] => 9/164608 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6096 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181173.pdf [firstpage_image] =>[orig_patent_app_number] => 164608 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164608
Power-on reset circuit Sep 30, 1998 Issued
Array ( [id] => 4225705 [patent_doc_number] => 06087896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Compensation technique using MOS capacitance' [patent_app_type] => 1 [patent_app_number] => 9/163789 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2462 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087896.pdf [firstpage_image] =>[orig_patent_app_number] => 163789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163789
Compensation technique using MOS capacitance Sep 29, 1998 Issued
Array ( [id] => 4139566 [patent_doc_number] => 06147518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Current comparator' [patent_app_type] => 1 [patent_app_number] => 9/162838 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2089 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147518.pdf [firstpage_image] =>[orig_patent_app_number] => 162838 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162838
Current comparator Sep 28, 1998 Issued
Array ( [id] => 4367042 [patent_doc_number] => 06191623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Multi-input comparator' [patent_app_type] => 1 [patent_app_number] => 9/162851 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 23 [patent_no_of_words] => 4242 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191623.pdf [firstpage_image] =>[orig_patent_app_number] => 162851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162851
Multi-input comparator Sep 28, 1998 Issued
Array ( [id] => 4311693 [patent_doc_number] => 06188255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Configurable clock generator' [patent_app_type] => 1 [patent_app_number] => 9/161821 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188255.pdf [firstpage_image] =>[orig_patent_app_number] => 161821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161821
Configurable clock generator Sep 27, 1998 Issued
Array ( [id] => 4160846 [patent_doc_number] => 06124747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Output buffer circuit capable of controlling through rate' [patent_app_type] => 1 [patent_app_number] => 9/159546 [patent_app_country] => US [patent_app_date] => 1998-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7384 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124747.pdf [firstpage_image] =>[orig_patent_app_number] => 159546 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159546
Output buffer circuit capable of controlling through rate Sep 23, 1998 Issued
Menu