
Ryan H. Ellis
Examiner (ID: 365)
| Most Active Art Unit | 3745 |
| Art Unit(s) | 3745 |
| Total Applications | 361 |
| Issued Applications | 222 |
| Pending Applications | 6 |
| Abandoned Applications | 135 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4163940
[patent_doc_number] => 06104229
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'High voltage tolerable input buffer and method for operating same'
[patent_app_type] => 1
[patent_app_number] => 8/649898
[patent_app_country] => US
[patent_app_date] => 1996-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4254
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/104/06104229.pdf
[firstpage_image] =>[orig_patent_app_number] => 649898
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/649898 | High voltage tolerable input buffer and method for operating same | May 1, 1996 | Issued |
Array
(
[id] => 3848494
[patent_doc_number] => 05708375
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Minimum pulse width detector for a measurement instrument'
[patent_app_type] => 1
[patent_app_number] => 8/661662
[patent_app_country] => US
[patent_app_date] => 1996-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2373
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/708/05708375.pdf
[firstpage_image] =>[orig_patent_app_number] => 661662
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/661662 | Minimum pulse width detector for a measurement instrument | Apr 28, 1996 | Issued |
Array
(
[id] => 3734724
[patent_doc_number] => 05703523
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Filter circuit'
[patent_app_type] => 1
[patent_app_number] => 8/641076
[patent_app_country] => US
[patent_app_date] => 1996-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3938
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/703/05703523.pdf
[firstpage_image] =>[orig_patent_app_number] => 641076
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/641076 | Filter circuit | Apr 25, 1996 | Issued |
Array
(
[id] => 3831876
[patent_doc_number] => 05731732
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Gate drive technique for a bidirectional blocking lateral MOSFET'
[patent_app_type] => 1
[patent_app_number] => 8/636258
[patent_app_country] => US
[patent_app_date] => 1996-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 31
[patent_no_of_words] => 6954
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/731/05731732.pdf
[firstpage_image] =>[orig_patent_app_number] => 636258
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636258 | Gate drive technique for a bidirectional blocking lateral MOSFET | Apr 21, 1996 | Issued |
Array
(
[id] => 3784976
[patent_doc_number] => 05818292
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Bandgap reference circuit'
[patent_app_type] => 1
[patent_app_number] => 8/859305
[patent_app_country] => US
[patent_app_date] => 1996-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3481
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/818/05818292.pdf
[firstpage_image] =>[orig_patent_app_number] => 859305
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/859305 | Bandgap reference circuit | Apr 1, 1996 | Issued |
Array
(
[id] => 3734679
[patent_doc_number] => 05703520
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Integrated inductive load snubbing device using a multi-collector transistor'
[patent_app_type] => 1
[patent_app_number] => 8/617705
[patent_app_country] => US
[patent_app_date] => 1996-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5317
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/703/05703520.pdf
[firstpage_image] =>[orig_patent_app_number] => 617705
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/617705 | Integrated inductive load snubbing device using a multi-collector transistor | Mar 31, 1996 | Issued |
Array
(
[id] => 1472227
[patent_doc_number] => 06407594
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-18
[patent_title] => 'Zero bias current driver control circuit'
[patent_app_type] => B1
[patent_app_number] => 08/621767
[patent_app_country] => US
[patent_app_date] => 1996-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2231
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 6
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/407/06407594.pdf
[firstpage_image] =>[orig_patent_app_number] => 08621767
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/621767 | Zero bias current driver control circuit | Mar 21, 1996 | Issued |
Array
(
[id] => 3693359
[patent_doc_number] => 05696462
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Serial clock synchronization circuit'
[patent_app_type] => 1
[patent_app_number] => 8/620703
[patent_app_country] => US
[patent_app_date] => 1996-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1907
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/696/05696462.pdf
[firstpage_image] =>[orig_patent_app_number] => 620703
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/620703 | Serial clock synchronization circuit | Mar 20, 1996 | Issued |
Array
(
[id] => 4063535
[patent_doc_number] => 05864254
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Differential amplifier circuit with enlarged range for source voltage and semiconductor device using same'
[patent_app_type] => 1
[patent_app_number] => 8/617583
[patent_app_country] => US
[patent_app_date] => 1996-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2757
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/864/05864254.pdf
[firstpage_image] =>[orig_patent_app_number] => 617583
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/617583 | Differential amplifier circuit with enlarged range for source voltage and semiconductor device using same | Mar 18, 1996 | Issued |
| 08/610643 | IC DEVICE TEMPERATURE COMPENSATION CIRCUIT AND METHOD | Mar 3, 1996 | Abandoned |
Array
(
[id] => 3837367
[patent_doc_number] => 05760639
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Voltage and current reference circuit with a low temperature coefficient'
[patent_app_type] => 1
[patent_app_number] => 8/610022
[patent_app_country] => US
[patent_app_date] => 1996-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4093
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/760/05760639.pdf
[firstpage_image] =>[orig_patent_app_number] => 610022
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/610022 | Voltage and current reference circuit with a low temperature coefficient | Mar 3, 1996 | Issued |
Array
(
[id] => 3817970
[patent_doc_number] => 05812001
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Power-on reset circuit for resetting semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/609911
[patent_app_country] => US
[patent_app_date] => 1996-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4541
[patent_no_of_claims] => 25
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/812/05812001.pdf
[firstpage_image] =>[orig_patent_app_number] => 609911
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/609911 | Power-on reset circuit for resetting semiconductor integrated circuit | Feb 28, 1996 | Issued |
Array
(
[id] => 3767384
[patent_doc_number] => 05742204
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Digitally programmable differential attenuator with tracking common mode reference'
[patent_app_type] => 1
[patent_app_number] => 8/608812
[patent_app_country] => US
[patent_app_date] => 1996-02-29
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742204.pdf
[firstpage_image] =>[orig_patent_app_number] => 608812
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/608812 | Digitally programmable differential attenuator with tracking common mode reference | Feb 28, 1996 | Issued |
Array
(
[id] => 3639827
[patent_doc_number] => 05631595
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Voltage signal line driver comprising a push-pull bridge amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/607619
[patent_app_country] => US
[patent_app_date] => 1996-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/631/05631595.pdf
[firstpage_image] =>[orig_patent_app_number] => 607619
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/607619 | Voltage signal line driver comprising a push-pull bridge amplifier | Feb 26, 1996 | Issued |
Array
(
[id] => 3796711
[patent_doc_number] => 05841317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Differential amplifier circuit with a high through put rate and reduced power consumption'
[patent_app_type] => 1
[patent_app_number] => 8/606945
[patent_app_country] => US
[patent_app_date] => 1996-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 10731
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841317.pdf
[firstpage_image] =>[orig_patent_app_number] => 606945
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/606945 | Differential amplifier circuit with a high through put rate and reduced power consumption | Feb 25, 1996 | Issued |
Array
(
[id] => 4015228
[patent_doc_number] => 05889425
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Analog multiplier using quadritail circuits'
[patent_app_type] => 1
[patent_app_number] => 8/604292
[patent_app_country] => US
[patent_app_date] => 1996-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[pdf_file] => patents/05/889/05889425.pdf
[firstpage_image] =>[orig_patent_app_number] => 604292
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/604292 | Analog multiplier using quadritail circuits | Feb 20, 1996 | Issued |
Array
(
[id] => 3792638
[patent_doc_number] => 05736884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Device for generating a control signal dependent on a variable resistance value and apparatus comprising such device'
[patent_app_type] => 1
[patent_app_number] => 8/601927
[patent_app_country] => US
[patent_app_date] => 1996-02-15
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4979
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/736/05736884.pdf
[firstpage_image] =>[orig_patent_app_number] => 601927
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/601927 | Device for generating a control signal dependent on a variable resistance value and apparatus comprising such device | Feb 14, 1996 | Issued |
Array
(
[id] => 3752519
[patent_doc_number] => 05717357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Output circuit for selectively outputting a signal at one of two voltage levels'
[patent_app_type] => 1
[patent_app_number] => 8/599943
[patent_app_country] => US
[patent_app_date] => 1996-02-14
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717357.pdf
[firstpage_image] =>[orig_patent_app_number] => 599943
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/599943 | Output circuit for selectively outputting a signal at one of two voltage levels | Feb 13, 1996 | Issued |
Array
(
[id] => 3792663
[patent_doc_number] => 05736886
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Input clamping method and apparatus with a correlated double-sampling circuit'
[patent_app_type] => 1
[patent_app_number] => 8/596029
[patent_app_country] => US
[patent_app_date] => 1996-02-06
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[pdf_file] => patents/05/736/05736886.pdf
[firstpage_image] =>[orig_patent_app_number] => 596029
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/596029 | Input clamping method and apparatus with a correlated double-sampling circuit | Feb 5, 1996 | Issued |
Array
(
[id] => 3885243
[patent_doc_number] => 05729167
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Low power consumption switch interface circuit'
[patent_app_type] => 1
[patent_app_number] => 8/595324
[patent_app_country] => US
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[pdf_file] => patents/05/729/05729167.pdf
[firstpage_image] =>[orig_patent_app_number] => 595324
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/595324 | Low power consumption switch interface circuit | Jan 31, 1996 | Issued |