Ryan Johnson

Array ( [id] => 20085800 [patent_doc_number] => 20250215736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => Wireless Movable Barrier Operating Systems and Methods [patent_app_type] => utility [patent_app_number] => 18/399176 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20070454 [patent_doc_number] => 20250208676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => VOLTAGE MARGIN OPTIMIZATION BASED ON WORKLOAD SENSITIVITY [patent_app_type] => utility [patent_app_number] => 18/395483 [patent_app_country] => US [patent_app_date] => 2023-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20388222 [patent_doc_number] => 12487948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Memory die interconnections to physical layer interfaces [patent_app_type] => utility [patent_app_number] => 18/540427 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20061599 [patent_doc_number] => 20250199821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => DC-SCM UNDISCOVERABLE DEVICE CONFIGURATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/538678 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20637042 [patent_doc_number] => 12597931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Clock insertion delay systems and methods [patent_app_type] => utility [patent_app_number] => 18/526943 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20461078 [patent_doc_number] => 20260010506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => HUMAN-MACHINE INTERFACE WITH A SECURE CONNECTION [patent_app_type] => utility [patent_app_number] => 19/134206 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19134206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19162134 [patent_doc_number] => 20240154841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SYSTEMS, DEVICES AND METHODS FOR AUTOMATICALLY ADDRESSING SERIALLY CONNECTED SLAVE DEVICES [patent_app_type] => utility [patent_app_number] => 18/507245 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19250763 [patent_doc_number] => 20240201753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Hardware receiver and support set for Internet of Things (IoT) system developers [patent_app_type] => utility [patent_app_number] => 18/502192 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20673311 [patent_doc_number] => 12613823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Modular communication system and method for operating the communication system [patent_app_type] => utility [patent_app_number] => 18/501232 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1101 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20009684 [patent_doc_number] => 20250147906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => CLOSED-LOOP TIMING CONTROL USING ACTIVE RE-TRAINING ENGINES IN MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/386464 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19994670 [patent_doc_number] => 20250132892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => ADAPTIVE CLOCK GENERATION FOR SERIAL LINKS [patent_app_type] => utility [patent_app_number] => 18/492126 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19942074 [patent_doc_number] => 12314203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Can controller, can device and method for the can controller [patent_app_type] => utility [patent_app_number] => 18/484316 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6093 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18904778 [patent_doc_number] => 20240020263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => CHIP HAVING DUAL-MODE DEVICE THAT SWITCHES BETWEEN ROOT COMPLEX MODE AND ENDPOINT MODE IN DIFFERENT SYSTEM STAGES AND ASSOCIATED COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 18/373968 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20745341 [patent_doc_number] => 12645251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Offloaded intra-system synchronization [patent_app_type] => utility [patent_app_number] => 18/470452 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1069 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20481679 [patent_doc_number] => 12530154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Solid state drive multi-card adapter with integrated processing [patent_app_type] => utility [patent_app_number] => 18/370871 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18370871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881447 [patent_doc_number] => 20240004816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => INTERFACE METHOD FOR TRANSMITTING AND RECIEVING DATA BETWEEN FUNCTIONAL BLOCKS IN SYSTEM ON CHIP, AND SYSTEM ON CHIP USING SAME [patent_app_type] => utility [patent_app_number] => 18/369345 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20265785 [patent_doc_number] => 12436776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Distributing endpoint devices configuration via coordinator device [patent_app_type] => utility [patent_app_number] => 18/468303 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19006033 [patent_doc_number] => 20240070104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => HOT-PLUGGING EDGE COMPUTING TERMINAL HARDWARE ARCHITECTURE AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/238537 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19802301 [patent_doc_number] => 20250068226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => PHY LANES DISABLING FOR POWER EFFICIENCY [patent_app_type] => utility [patent_app_number] => 18/455958 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20281715 [patent_doc_number] => 20250306957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => PAGE DISPLAY METHOD AND APPARATUS, STORAGE MEDIUM, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/865305 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18865305 [rel_patent_id] =>[rel_patent_doc_number] =>)