Search

Ryan Johnson

Examiner (ID: 12089)

Most Active Art Unit
2849
Art Unit(s)
2817, 2843, 2849, 2842, 2836
Total Applications
1604
Issued Applications
1323
Pending Applications
83
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 186382 [patent_doc_number] => 07646257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Method and apparatus to facilitate the provision and use of a plurality of varactors with a plurality of switches' [patent_app_type] => utility [patent_app_number] => 11/621769 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3752 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646257.pdf [firstpage_image] =>[orig_patent_app_number] => 11621769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/621769
Method and apparatus to facilitate the provision and use of a plurality of varactors with a plurality of switches Jan 9, 2007 Issued
Array ( [id] => 4925592 [patent_doc_number] => 20080164955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'VOLTAGE CONTROLLED OSCILLATOR CIRCUITS AND METHODS USING VARIABLE CAPACITANCE DEGENERATION FOR INCREASED TUNING RANGE' [patent_app_type] => utility [patent_app_number] => 11/619765 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3202 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20080164955.pdf [firstpage_image] =>[orig_patent_app_number] => 11619765 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619765
VOLTAGE CONTROLLED OSCILLATOR CIRCUITS AND METHODS USING VARIABLE CAPACITANCE DEGENERATION FOR INCREASED TUNING RANGE Jan 3, 2007 Abandoned
Array ( [id] => 5102685 [patent_doc_number] => 20070185947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Frequency synthesizer' [patent_app_type] => utility [patent_app_number] => 11/648663 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11877 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20070185947.pdf [firstpage_image] =>[orig_patent_app_number] => 11648663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648663
Frequency synthesizer Jan 2, 2007 Abandoned
Array ( [id] => 4580692 [patent_doc_number] => 07825738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method and system for implementing a low power, high performance fractional-N PLL' [patent_app_type] => utility [patent_app_number] => 11/618651 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/825/07825738.pdf [firstpage_image] =>[orig_patent_app_number] => 11618651 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618651
Method and system for implementing a low power, high performance fractional-N PLL Dec 28, 2006 Issued
Array ( [id] => 114383 [patent_doc_number] => 07714665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Harmonic characterization and correction of device mismatch' [patent_app_type] => utility [patent_app_number] => 11/618605 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 9774 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/714/07714665.pdf [firstpage_image] =>[orig_patent_app_number] => 11618605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618605
Harmonic characterization and correction of device mismatch Dec 28, 2006 Issued
Array ( [id] => 4783204 [patent_doc_number] => 20080136533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'METHOD AND SYSTEM FOR FAST PLL CLOSE-LOOP SETTLING AFTER OPEN-LOOP VCO CALIBRATION' [patent_app_type] => utility [patent_app_number] => 11/618715 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20080136533.pdf [firstpage_image] =>[orig_patent_app_number] => 11618715 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618715
Method and system for fast PLL close-loop settling after open-loop VCO calibration Dec 28, 2006 Issued
Array ( [id] => 7529070 [patent_doc_number] => 08045674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Method and system for use of TSPC logic for high-speed multi-modulus divider in PLL' [patent_app_type] => utility [patent_app_number] => 11/618718 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8558 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/045/08045674.pdf [firstpage_image] =>[orig_patent_app_number] => 11618718 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618718
Method and system for use of TSPC logic for high-speed multi-modulus divider in PLL Dec 28, 2006 Issued
Array ( [id] => 4749794 [patent_doc_number] => 20080157865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'TUNABLE CAPACITANCE MULTIPLIER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/617813 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4613 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157865.pdf [firstpage_image] =>[orig_patent_app_number] => 11617813 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/617813
TUNABLE CAPACITANCE MULTIPLIER CIRCUIT Dec 28, 2006 Abandoned
Array ( [id] => 253282 [patent_doc_number] => 07579918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Clock generator with reduced electromagnetic interference for DC-DC converters' [patent_app_type] => utility [patent_app_number] => 11/647626 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2152 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579918.pdf [firstpage_image] =>[orig_patent_app_number] => 11647626 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647626
Clock generator with reduced electromagnetic interference for DC-DC converters Dec 27, 2006 Issued
Array ( [id] => 304165 [patent_doc_number] => 07535306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Oscillator coupling system' [patent_app_type] => utility [patent_app_number] => 11/614465 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3834 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535306.pdf [firstpage_image] =>[orig_patent_app_number] => 11614465 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614465
Oscillator coupling system Dec 20, 2006 Issued
Array ( [id] => 4864393 [patent_doc_number] => 20080143452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Systems and Methods with Reduced Reference Spurs Using a Crystal Oscillator For Broadband Communications' [patent_app_type] => utility [patent_app_number] => 11/612666 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7999 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20080143452.pdf [firstpage_image] =>[orig_patent_app_number] => 11612666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612666
Systems and methods with reduced reference spurs using a crystal oscillator for broadband communications Dec 18, 2006 Issued
Array ( [id] => 323224 [patent_doc_number] => 07518459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Harmonic-rejection modulation device' [patent_app_type] => utility [patent_app_number] => 11/611256 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2750 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518459.pdf [firstpage_image] =>[orig_patent_app_number] => 11611256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611256
Harmonic-rejection modulation device Dec 14, 2006 Issued
Array ( [id] => 4731810 [patent_doc_number] => 20080048788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'FREQUENCY TUNING METHOD FOR VOLTAGE CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP USING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/610012 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5141 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048788.pdf [firstpage_image] =>[orig_patent_app_number] => 11610012 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/610012
FREQUENCY TUNING METHOD FOR VOLTAGE CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP USING THE SAME Dec 12, 2006 Abandoned
Array ( [id] => 4986423 [patent_doc_number] => 20070152761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Voltage controlled oscillator with variable control sensitivity' [patent_app_type] => utility [patent_app_number] => 11/636977 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2679 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20070152761.pdf [firstpage_image] =>[orig_patent_app_number] => 11636977 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636977
Voltage controlled oscillator with variable control sensitivity Dec 11, 2006 Abandoned
Array ( [id] => 5020116 [patent_doc_number] => 20070146082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Frequency synthesizer, wireless communications device, and control method' [patent_app_type] => utility [patent_app_number] => 11/635084 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9144 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20070146082.pdf [firstpage_image] =>[orig_patent_app_number] => 11635084 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/635084
Frequency synthesizer, wireless communications device, and control method Dec 6, 2006 Abandoned
Array ( [id] => 114393 [patent_doc_number] => 07714675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'All digital Class-D modulator and its saturation protection techniques' [patent_app_type] => utility [patent_app_number] => 11/566995 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4730 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/714/07714675.pdf [firstpage_image] =>[orig_patent_app_number] => 11566995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/566995
All digital Class-D modulator and its saturation protection techniques Dec 4, 2006 Issued
Array ( [id] => 160591 [patent_doc_number] => 07675377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Voltage controlled oscillator' [patent_app_type] => utility [patent_app_number] => 11/918601 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 11342 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/675/07675377.pdf [firstpage_image] =>[orig_patent_app_number] => 11918601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/918601
Voltage controlled oscillator Nov 28, 2006 Issued
Array ( [id] => 5093275 [patent_doc_number] => 20070114884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'METHOD OF MANUFACTURING SURFACE MOUNT TYPE CRYSTAL OSCILLATOR' [patent_app_type] => utility [patent_app_number] => 11/562279 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2507 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20070114884.pdf [firstpage_image] =>[orig_patent_app_number] => 11562279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562279
Method of manufacturing surface mount type crystal oscillator Nov 20, 2006 Issued
Array ( [id] => 4969056 [patent_doc_number] => 20070109058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Differential amplifier, differential amplifying method, and phase locked loop and delay locked loop using the same' [patent_app_type] => utility [patent_app_number] => 11/594448 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109058.pdf [firstpage_image] =>[orig_patent_app_number] => 11594448 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594448
Differential amplifier, differential amplifying method, and phase locked loop and delay locked loop using the same Nov 7, 2006 Issued
Array ( [id] => 4986428 [patent_doc_number] => 20070152766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'FREQUENCY MODULATED OUTPUT CLOCK FROM A DIGITAL FREQUENCY/PHASE LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 11/557721 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5515 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20070152766.pdf [firstpage_image] =>[orig_patent_app_number] => 11557721 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557721
Frequency modulated output clock from a digital frequency/phase locked loop Nov 7, 2006 Issued
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