
Ryan Johnson
Examiner (ID: 12089)
| Most Active Art Unit | 2849 |
| Art Unit(s) | 2817, 2843, 2849, 2842, 2836 |
| Total Applications | 1604 |
| Issued Applications | 1323 |
| Pending Applications | 83 |
| Abandoned Applications | 220 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 186382
[patent_doc_number] => 07646257
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Method and apparatus to facilitate the provision and use of a plurality of varactors with a plurality of switches'
[patent_app_type] => utility
[patent_app_number] => 11/621769
[patent_app_country] => US
[patent_app_date] => 2007-01-10
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/646/07646257.pdf
[firstpage_image] =>[orig_patent_app_number] => 11621769
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/621769 | Method and apparatus to facilitate the provision and use of a plurality of varactors with a plurality of switches | Jan 9, 2007 | Issued |
Array
(
[id] => 4925592
[patent_doc_number] => 20080164955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-10
[patent_title] => 'VOLTAGE CONTROLLED OSCILLATOR CIRCUITS AND METHODS USING VARIABLE CAPACITANCE DEGENERATION FOR INCREASED TUNING RANGE'
[patent_app_type] => utility
[patent_app_number] => 11/619765
[patent_app_country] => US
[patent_app_date] => 2007-01-04
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11619765
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/619765 | VOLTAGE CONTROLLED OSCILLATOR CIRCUITS AND METHODS USING VARIABLE CAPACITANCE DEGENERATION FOR INCREASED TUNING RANGE | Jan 3, 2007 | Abandoned |
Array
(
[id] => 5102685
[patent_doc_number] => 20070185947
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[patent_kind] => A1
[patent_issue_date] => 2007-08-09
[patent_title] => 'Frequency synthesizer'
[patent_app_type] => utility
[patent_app_number] => 11/648663
[patent_app_country] => US
[patent_app_date] => 2007-01-03
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[firstpage_image] =>[orig_patent_app_number] => 11648663
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/648663 | Frequency synthesizer | Jan 2, 2007 | Abandoned |
Array
(
[id] => 4580692
[patent_doc_number] => 07825738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-02
[patent_title] => 'Method and system for implementing a low power, high performance fractional-N PLL'
[patent_app_type] => utility
[patent_app_number] => 11/618651
[patent_app_country] => US
[patent_app_date] => 2006-12-29
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[patent_drawing_sheets_cnt] => 4
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[firstpage_image] =>[orig_patent_app_number] => 11618651
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618651 | Method and system for implementing a low power, high performance fractional-N PLL | Dec 28, 2006 | Issued |
Array
(
[id] => 114383
[patent_doc_number] => 07714665
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[patent_issue_date] => 2010-05-11
[patent_title] => 'Harmonic characterization and correction of device mismatch'
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[patent_app_number] => 11/618605
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[firstpage_image] =>[orig_patent_app_number] => 11618605
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618605 | Harmonic characterization and correction of device mismatch | Dec 28, 2006 | Issued |
Array
(
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[patent_title] => 'METHOD AND SYSTEM FOR FAST PLL CLOSE-LOOP SETTLING AFTER OPEN-LOOP VCO CALIBRATION'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11618715
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618715 | Method and system for fast PLL close-loop settling after open-loop VCO calibration | Dec 28, 2006 | Issued |
Array
(
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[patent_doc_number] => 08045674
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[patent_issue_date] => 2011-10-25
[patent_title] => 'Method and system for use of TSPC logic for high-speed multi-modulus divider in PLL'
[patent_app_type] => utility
[patent_app_number] => 11/618718
[patent_app_country] => US
[patent_app_date] => 2006-12-29
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[pdf_file] => patents/08/045/08045674.pdf
[firstpage_image] =>[orig_patent_app_number] => 11618718
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618718 | Method and system for use of TSPC logic for high-speed multi-modulus divider in PLL | Dec 28, 2006 | Issued |
Array
(
[id] => 4749794
[patent_doc_number] => 20080157865
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'TUNABLE CAPACITANCE MULTIPLIER CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/617813
[patent_app_country] => US
[patent_app_date] => 2006-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617813 | TUNABLE CAPACITANCE MULTIPLIER CIRCUIT | Dec 28, 2006 | Abandoned |
Array
(
[id] => 253282
[patent_doc_number] => 07579918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-25
[patent_title] => 'Clock generator with reduced electromagnetic interference for DC-DC converters'
[patent_app_type] => utility
[patent_app_number] => 11/647626
[patent_app_country] => US
[patent_app_date] => 2006-12-28
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/07/579/07579918.pdf
[firstpage_image] =>[orig_patent_app_number] => 11647626
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/647626 | Clock generator with reduced electromagnetic interference for DC-DC converters | Dec 27, 2006 | Issued |
Array
(
[id] => 304165
[patent_doc_number] => 07535306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-19
[patent_title] => 'Oscillator coupling system'
[patent_app_type] => utility
[patent_app_number] => 11/614465
[patent_app_country] => US
[patent_app_date] => 2006-12-21
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[firstpage_image] =>[orig_patent_app_number] => 11614465
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/614465 | Oscillator coupling system | Dec 20, 2006 | Issued |
Array
(
[id] => 4864393
[patent_doc_number] => 20080143452
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[patent_kind] => A1
[patent_issue_date] => 2008-06-19
[patent_title] => 'Systems and Methods with Reduced Reference Spurs Using a Crystal Oscillator For Broadband Communications'
[patent_app_type] => utility
[patent_app_number] => 11/612666
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[firstpage_image] =>[orig_patent_app_number] => 11612666
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/612666 | Systems and methods with reduced reference spurs using a crystal oscillator for broadband communications | Dec 18, 2006 | Issued |
Array
(
[id] => 323224
[patent_doc_number] => 07518459
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[patent_title] => 'Harmonic-rejection modulation device'
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[patent_app_number] => 11/611256
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/611256 | Harmonic-rejection modulation device | Dec 14, 2006 | Issued |
Array
(
[id] => 4731810
[patent_doc_number] => 20080048788
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[patent_title] => 'FREQUENCY TUNING METHOD FOR VOLTAGE CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP USING THE SAME'
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[patent_app_number] => 11/610012
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/610012 | FREQUENCY TUNING METHOD FOR VOLTAGE CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP USING THE SAME | Dec 12, 2006 | Abandoned |
Array
(
[id] => 4986423
[patent_doc_number] => 20070152761
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[patent_issue_date] => 2007-07-05
[patent_title] => 'Voltage controlled oscillator with variable control sensitivity'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/635084 | Frequency synthesizer, wireless communications device, and control method | Dec 6, 2006 | Abandoned |
Array
(
[id] => 114393
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[patent_issue_date] => 2010-05-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/566995 | All digital Class-D modulator and its saturation protection techniques | Dec 4, 2006 | Issued |
Array
(
[id] => 160591
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Array
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Array
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[patent_title] => 'FREQUENCY MODULATED OUTPUT CLOCK FROM A DIGITAL FREQUENCY/PHASE LOCKED LOOP'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/557721 | Frequency modulated output clock from a digital frequency/phase locked loop | Nov 7, 2006 | Issued |