
Ryan M. Stiglic
Examiner (ID: 10733)
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2111, 6213, 2185, 2112, OPQA |
| Total Applications | 589 |
| Issued Applications | 426 |
| Pending Applications | 10 |
| Abandoned Applications | 155 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8149302
[patent_doc_number] => 08166319
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-24
[patent_title] => 'Methods and systems for use-case aware voltage selection'
[patent_app_type] => utility
[patent_app_number] => 12/496879
[patent_app_country] => US
[patent_app_date] => 2009-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 6220
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[pdf_file] => patents/08/166/08166319.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/496879 | Methods and systems for use-case aware voltage selection | Jul 1, 2009 | Issued |
Array
(
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[patent_doc_number] => 20100332711
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[patent_kind] => A1
[patent_issue_date] => 2010-12-30
[patent_title] => 'Display device with built in hard drive docking station'
[patent_app_type] => utility
[patent_app_number] => 12/459331
[patent_app_country] => US
[patent_app_date] => 2009-06-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/459331 | Display device with built in hard drive docking station | Jun 29, 2009 | Abandoned |
Array
(
[id] => 6363247
[patent_doc_number] => 20100332876
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[patent_kind] => A1
[patent_issue_date] => 2010-12-30
[patent_title] => 'REDUCING POWER CONSUMPTION OF COMPUTING DEVICES BY FORECASTING COMPUTING PERFORMANCE NEEDS'
[patent_app_type] => utility
[patent_app_number] => 12/493058
[patent_app_country] => US
[patent_app_date] => 2009-06-26
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/493058 | Reducing power consumption of computing devices by forecasting computing performance needs | Jun 25, 2009 | Issued |
Array
(
[id] => 7730459
[patent_doc_number] => 20120014390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-19
[patent_title] => 'PROCESSOR TOPOLOGY SWITCHES'
[patent_app_type] => utility
[patent_app_number] => 13/258903
[patent_app_country] => US
[patent_app_date] => 2009-06-18
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/258903 | Processor topology switches | Jun 17, 2009 | Issued |
Array
(
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[patent_doc_number] => 08131901
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[patent_issue_date] => 2012-03-06
[patent_title] => 'Interrupt control for virtual processing apparatus'
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Array
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[patent_issue_date] => 2010-12-02
[patent_title] => 'METHODS AND APPARATUS FOR CONTROL CONFIGURATION WITH CONTROL OBJECTS THAT ARE FIELDBUS PROTOCOL-AWARE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/474942 | Methods and apparatus for control configuration with control objects that are fieldbus protocol-aware | May 28, 2009 | Issued |
Array
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[patent_title] => 'Asynchronous circuit insensitive to delays with time delay insertion circuit'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/453826 | Asynchronous circuit insensitive to delays with time delay insertion circuit | May 21, 2009 | Issued |
Array
(
[id] => 7779774
[patent_doc_number] => 08122177
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[patent_issue_date] => 2012-02-21
[patent_title] => 'Direct memory access technique for use with PCIe endpoints'
[patent_app_type] => utility
[patent_app_number] => 12/468340
[patent_app_country] => US
[patent_app_date] => 2009-05-19
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[pdf_file] => patents/08/122/08122177.pdf
[firstpage_image] =>[orig_patent_app_number] => 12468340
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/468340 | Direct memory access technique for use with PCIe endpoints | May 18, 2009 | Issued |
Array
(
[id] => 9940637
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[patent_title] => 'I/O connection system, method and program'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/736808 | I/O connection system, method and program | May 13, 2009 | Issued |
Array
(
[id] => 6241075
[patent_doc_number] => 20100268969
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[patent_kind] => A1
[patent_issue_date] => 2010-10-21
[patent_title] => 'POWER SUPPLY CONVERTING CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/464086
[patent_app_country] => US
[patent_app_date] => 2009-05-11
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/464086 | Power supply converting circuit | May 10, 2009 | Issued |
Array
(
[id] => 5317678
[patent_doc_number] => 20090282276
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[patent_title] => 'Peripheral device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/387916 | Peripheral device | May 7, 2009 | Abandoned |
Array
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[patent_title] => 'NORTH-BRIDGE TO SOUTH-BRIDGE PROTOCOL FOR PLACING PROCESSOR IN LOW POWER STATE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/436439 | North-bridge to south-bridge protocol for placing processor in low power state | May 5, 2009 | Issued |
Array
(
[id] => 6533043
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[patent_issue_date] => 2010-11-11
[patent_title] => 'METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN ASYNCHRONOUS CLOCK DOMAINS'
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Array
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[patent_title] => 'NETWORK RANGE EXTENDER DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/429260 | Method and system of improving memory power efficiency | Apr 23, 2009 | Issued |
Array
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Array
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