Search

Ryan M. Stiglic

Examiner (ID: 10733)

Most Active Art Unit
2111
Art Unit(s)
2111, 6213, 2185, 2112, OPQA
Total Applications
589
Issued Applications
426
Pending Applications
10
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8149302 [patent_doc_number] => 08166319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Methods and systems for use-case aware voltage selection' [patent_app_type] => utility [patent_app_number] => 12/496879 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6220 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166319.pdf [firstpage_image] =>[orig_patent_app_number] => 12496879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496879
Methods and systems for use-case aware voltage selection Jul 1, 2009 Issued
Array ( [id] => 6362128 [patent_doc_number] => 20100332711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Display device with built in hard drive docking station' [patent_app_type] => utility [patent_app_number] => 12/459331 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1951 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332711.pdf [firstpage_image] =>[orig_patent_app_number] => 12459331 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/459331
Display device with built in hard drive docking station Jun 29, 2009 Abandoned
Array ( [id] => 6363247 [patent_doc_number] => 20100332876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'REDUCING POWER CONSUMPTION OF COMPUTING DEVICES BY FORECASTING COMPUTING PERFORMANCE NEEDS' [patent_app_type] => utility [patent_app_number] => 12/493058 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332876.pdf [firstpage_image] =>[orig_patent_app_number] => 12493058 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493058
Reducing power consumption of computing devices by forecasting computing performance needs Jun 25, 2009 Issued
Array ( [id] => 7730459 [patent_doc_number] => 20120014390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'PROCESSOR TOPOLOGY SWITCHES' [patent_app_type] => utility [patent_app_number] => 13/258903 [patent_app_country] => US [patent_app_date] => 2009-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20120014390.pdf [firstpage_image] =>[orig_patent_app_number] => 13258903 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/258903
Processor topology switches Jun 17, 2009 Issued
Array ( [id] => 7803617 [patent_doc_number] => 08131901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Interrupt control for virtual processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/457263 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7265 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/131/08131901.pdf [firstpage_image] =>[orig_patent_app_number] => 12457263 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457263
Interrupt control for virtual processing apparatus Jun 3, 2009 Issued
Array ( [id] => 6406912 [patent_doc_number] => 20100305720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'METHODS AND APPARATUS FOR CONTROL CONFIGURATION WITH CONTROL OBJECTS THAT ARE FIELDBUS PROTOCOL-AWARE' [patent_app_type] => utility [patent_app_number] => 12/474942 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 46067 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0305/20100305720.pdf [firstpage_image] =>[orig_patent_app_number] => 12474942 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/474942
Methods and apparatus for control configuration with control objects that are fieldbus protocol-aware May 28, 2009 Issued
Array ( [id] => 8158304 [patent_doc_number] => 08171330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Asynchronous circuit insensitive to delays with time delay insertion circuit' [patent_app_type] => utility [patent_app_number] => 12/453826 [patent_app_country] => US [patent_app_date] => 2009-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5129 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171330.pdf [firstpage_image] =>[orig_patent_app_number] => 12453826 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453826
Asynchronous circuit insensitive to delays with time delay insertion circuit May 21, 2009 Issued
Array ( [id] => 7779774 [patent_doc_number] => 08122177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-21 [patent_title] => 'Direct memory access technique for use with PCIe endpoints' [patent_app_type] => utility [patent_app_number] => 12/468340 [patent_app_country] => US [patent_app_date] => 2009-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7651 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122177.pdf [firstpage_image] =>[orig_patent_app_number] => 12468340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/468340
Direct memory access technique for use with PCIe endpoints May 18, 2009 Issued
Array ( [id] => 9940637 [patent_doc_number] => 08990468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'I/O connection system, method and program' [patent_app_type] => utility [patent_app_number] => 12/736808 [patent_app_country] => US [patent_app_date] => 2009-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5877 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12736808 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/736808
I/O connection system, method and program May 13, 2009 Issued
Array ( [id] => 6241075 [patent_doc_number] => 20100268969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'POWER SUPPLY CONVERTING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/464086 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1767 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268969.pdf [firstpage_image] =>[orig_patent_app_number] => 12464086 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/464086
Power supply converting circuit May 10, 2009 Issued
Array ( [id] => 5317678 [patent_doc_number] => 20090282276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'Peripheral device' [patent_app_type] => utility [patent_app_number] => 12/387916 [patent_app_country] => US [patent_app_date] => 2009-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1688 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282276.pdf [firstpage_image] =>[orig_patent_app_number] => 12387916 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/387916
Peripheral device May 7, 2009 Abandoned
Array ( [id] => 6532753 [patent_doc_number] => 20100287394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'NORTH-BRIDGE TO SOUTH-BRIDGE PROTOCOL FOR PLACING PROCESSOR IN LOW POWER STATE' [patent_app_type] => utility [patent_app_number] => 12/436439 [patent_app_country] => US [patent_app_date] => 2009-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6478 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287394.pdf [firstpage_image] =>[orig_patent_app_number] => 12436439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/436439
North-bridge to south-bridge protocol for placing processor in low power state May 5, 2009 Issued
Array ( [id] => 6533043 [patent_doc_number] => 20100287401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN ASYNCHRONOUS CLOCK DOMAINS' [patent_app_type] => utility [patent_app_number] => 12/435550 [patent_app_country] => US [patent_app_date] => 2009-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287401.pdf [firstpage_image] =>[orig_patent_app_number] => 12435550 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/435550
Method and apparatus for transferring data between asynchronous clock domains May 4, 2009 Issued
Array ( [id] => 6592745 [patent_doc_number] => 20100274927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'NETWORK RANGE EXTENDER DEVICE' [patent_app_type] => utility [patent_app_number] => 12/430462 [patent_app_country] => US [patent_app_date] => 2009-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20100274927.pdf [firstpage_image] =>[orig_patent_app_number] => 12430462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/430462
Network range extender device Apr 26, 2009 Issued
Array ( [id] => 6395630 [patent_doc_number] => 20100164470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'METHOD AND SYSTEM OF IMPROVING MEMORY POWER EFFICIENCY' [patent_app_type] => utility [patent_app_number] => 12/429260 [patent_app_country] => US [patent_app_date] => 2009-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 718 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20100164470.pdf [firstpage_image] =>[orig_patent_app_number] => 12429260 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/429260
Method and system of improving memory power efficiency Apr 23, 2009 Issued
Array ( [id] => 6302201 [patent_doc_number] => 20100162016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'LOW POWER CONSUMPTION PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/427291 [patent_app_country] => US [patent_app_date] => 2009-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2902 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20100162016.pdf [firstpage_image] =>[orig_patent_app_number] => 12427291 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/427291
Low power consumption processor Apr 20, 2009 Issued
Array ( [id] => 6153826 [patent_doc_number] => 20110022876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'COMPUTER SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/922785 [patent_app_country] => US [patent_app_date] => 2009-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7647 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022876.pdf [firstpage_image] =>[orig_patent_app_number] => 12922785 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/922785
Computer system and operating method thereof Apr 7, 2009 Issued
Array ( [id] => 5497474 [patent_doc_number] => 20090265502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'SIGNAL PROCESSING DEVICE AND CONTROL METHOD, SIGNAL PROCESSING METHOD, PROGRAM, AND SIGNAL PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/416518 [patent_app_country] => US [patent_app_date] => 2009-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14907 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265502.pdf [firstpage_image] =>[orig_patent_app_number] => 12416518 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416518
Signal processing device and control method, signal processing method, program, and signal processing system Mar 31, 2009 Issued
Array ( [id] => 5475768 [patent_doc_number] => 20090248934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'INTERRUPT DISPATCHING METHOD IN MULTI-CORE ENVIRONMENT AND MULTI-CORE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/412286 [patent_app_country] => US [patent_app_date] => 2009-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20090248934.pdf [firstpage_image] =>[orig_patent_app_number] => 12412286 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/412286
Interrupt dispatching method in multi-core environment and multi-core processor Mar 25, 2009 Issued
Array ( [id] => 7779761 [patent_doc_number] => 08122171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Bus enumeration in a system with multiple buses' [patent_app_type] => utility [patent_app_number] => 12/408574 [patent_app_country] => US [patent_app_date] => 2009-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4428 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122171.pdf [firstpage_image] =>[orig_patent_app_number] => 12408574 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/408574
Bus enumeration in a system with multiple buses Mar 19, 2009 Issued
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