Search

Ryan M. Stiglic

Examiner (ID: 10733)

Most Active Art Unit
2111
Art Unit(s)
2111, 6213, 2185, 2112, OPQA
Total Applications
589
Issued Applications
426
Pending Applications
10
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6234342 [patent_doc_number] => 20100185877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'System and Method for Information Handling System Power Management by Variable Direct Current Input' [patent_app_type] => utility [patent_app_number] => 12/355045 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185877.pdf [firstpage_image] =>[orig_patent_app_number] => 12355045 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/355045
System and method for information handling system power management by variable direct current input Jan 15, 2009 Issued
Array ( [id] => 7686472 [patent_doc_number] => 20090177819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'INTEGRATED CIRCUIT CARDS INCLUDING MULTIPLE COMMUNICATION INTERFACES AND RELATED METHODS OF OPERATION' [patent_app_type] => utility [patent_app_number] => 12/349003 [patent_app_country] => US [patent_app_date] => 2009-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177819.pdf [firstpage_image] =>[orig_patent_app_number] => 12349003 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/349003
INTEGRATED CIRCUIT CARDS INCLUDING MULTIPLE COMMUNICATION INTERFACES AND RELATED METHODS OF OPERATION Jan 5, 2009 Abandoned
Array ( [id] => 5504003 [patent_doc_number] => 20090164691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'IO PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/338952 [patent_app_country] => US [patent_app_date] => 2008-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9445 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20090164691.pdf [firstpage_image] =>[orig_patent_app_number] => 12338952 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/338952
IO processor Dec 17, 2008 Issued
Array ( [id] => 6462991 [patent_doc_number] => 20100146166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'METHODS AND APPARATUSES FOR IMPROVING SATA TARGET DEVICE DETECTION' [patent_app_type] => utility [patent_app_number] => 12/332123 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2594 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146166.pdf [firstpage_image] =>[orig_patent_app_number] => 12332123 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332123
Methods and apparatuses for improving SATA target device detection Dec 9, 2008 Issued
Array ( [id] => 4462230 [patent_doc_number] => 07895376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Hardware configuration information system, method, and computer program product' [patent_app_type] => utility [patent_app_number] => 12/324329 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895376.pdf [firstpage_image] =>[orig_patent_app_number] => 12324329 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/324329
Hardware configuration information system, method, and computer program product Nov 25, 2008 Issued
Array ( [id] => 4527200 [patent_doc_number] => 07934033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'PCI-express function proxy' [patent_app_type] => utility [patent_app_number] => 12/265695 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934033.pdf [firstpage_image] =>[orig_patent_app_number] => 12265695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265695
PCI-express function proxy Nov 4, 2008 Issued
Array ( [id] => 6052107 [patent_doc_number] => 20110208889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'SATA/ESATA PORT CONFIGURATION' [patent_app_type] => utility [patent_app_number] => 13/125972 [patent_app_country] => US [patent_app_date] => 2008-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3869 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20110208889.pdf [firstpage_image] =>[orig_patent_app_number] => 13125972 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/125972
SATA/eSATA port configuration Oct 30, 2008 Issued
Array ( [id] => 8546404 [patent_doc_number] => 08321707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Main computer for vehicle and power management method thereof' [patent_app_type] => utility [patent_app_number] => 12/261070 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4688 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12261070 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/261070
Main computer for vehicle and power management method thereof Oct 29, 2008 Issued
Array ( [id] => 4636958 [patent_doc_number] => 08015423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-06 [patent_title] => 'Temporally normalized processor utilization' [patent_app_type] => utility [patent_app_number] => 12/261422 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1522 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015423.pdf [firstpage_image] =>[orig_patent_app_number] => 12261422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/261422
Temporally normalized processor utilization Oct 29, 2008 Issued
Array ( [id] => 7679712 [patent_doc_number] => 20100106875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'Technique for communicating interrupts in a computer system' [patent_app_type] => utility [patent_app_number] => 12/290208 [patent_app_country] => US [patent_app_date] => 2008-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3122 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20100106875.pdf [firstpage_image] =>[orig_patent_app_number] => 12290208 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/290208
Technique for communicating interrupts in a computer system Oct 27, 2008 Issued
Array ( [id] => 6368915 [patent_doc_number] => 20100088547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'COMPUTER MOTHERBOARD AND POWER-ON SELF-TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/257365 [patent_app_country] => US [patent_app_date] => 2008-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1072 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20100088547.pdf [firstpage_image] =>[orig_patent_app_number] => 12257365 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/257365
COMPUTER MOTHERBOARD AND POWER-ON SELF-TEST METHOD THEREOF Oct 22, 2008 Abandoned
Array ( [id] => 6623506 [patent_doc_number] => 20100100254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'System and Method for Adapting a Power Usage of a Server During a Data Center Cooling Failure' [patent_app_type] => utility [patent_app_number] => 12/255250 [patent_app_country] => US [patent_app_date] => 2008-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100254.pdf [firstpage_image] =>[orig_patent_app_number] => 12255250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/255250
System and method for adapting a power usage of a server during a data center cooling failure Oct 20, 2008 Issued
Array ( [id] => 6629046 [patent_doc_number] => 20100100750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'TECHNIQUES FOR ENSURING POWER DELIVERY OVER ONLY DATA-ACTIVE PAIRS OF DATA COMMUNICATIONS CABLING' [patent_app_type] => utility [patent_app_number] => 12/252533 [patent_app_country] => US [patent_app_date] => 2008-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4201 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100750.pdf [firstpage_image] =>[orig_patent_app_number] => 12252533 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/252533
Techniques for ensuring power delivery over only data-active pairs of data communications cabling Oct 15, 2008 Issued
Array ( [id] => 4621575 [patent_doc_number] => 08001306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Interface unit and communication system having a master/slave structure' [patent_app_type] => utility [patent_app_number] => 12/251028 [patent_app_country] => US [patent_app_date] => 2008-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8015 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001306.pdf [firstpage_image] =>[orig_patent_app_number] => 12251028 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/251028
Interface unit and communication system having a master/slave structure Oct 13, 2008 Issued
Array ( [id] => 7798443 [patent_doc_number] => 08127161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Data processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/250123 [patent_app_country] => US [patent_app_date] => 2008-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4809 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/127/08127161.pdf [firstpage_image] =>[orig_patent_app_number] => 12250123 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/250123
Data processing apparatus Oct 12, 2008 Issued
Array ( [id] => 6388426 [patent_doc_number] => 20100083027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'SERIAL-CONNECTED MEMORY SYSTEM WITH OUTPUT DELAY ADJUSTMENT' [patent_app_type] => utility [patent_app_number] => 12/241832 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11237 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083027.pdf [firstpage_image] =>[orig_patent_app_number] => 12241832 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/241832
Serial-connected memory system with output delay adjustment Sep 29, 2008 Issued
Array ( [id] => 4592772 [patent_doc_number] => 07853748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Method and apparatus to obtain code data for USB device' [patent_app_type] => utility [patent_app_number] => 12/242293 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4353 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853748.pdf [firstpage_image] =>[orig_patent_app_number] => 12242293 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242293
Method and apparatus to obtain code data for USB device Sep 29, 2008 Issued
Array ( [id] => 6388430 [patent_doc_number] => 20100083028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'SERIAL-CONNECTED MEMORY SYSTEM WITH DUTY CYCLE CORRECTION' [patent_app_type] => utility [patent_app_number] => 12/241960 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11594 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083028.pdf [firstpage_image] =>[orig_patent_app_number] => 12241960 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/241960
Serial-connected memory system with duty cycle correction Sep 29, 2008 Issued
Array ( [id] => 7803749 [patent_doc_number] => 08132033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Storage system' [patent_app_type] => utility [patent_app_number] => 12/236529 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9790 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/132/08132033.pdf [firstpage_image] =>[orig_patent_app_number] => 12236529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/236529
Storage system Sep 23, 2008 Issued
Array ( [id] => 58456 [patent_doc_number] => 07769941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'USB matrix switch system' [patent_app_type] => utility [patent_app_number] => 12/235815 [patent_app_country] => US [patent_app_date] => 2008-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3452 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/769/07769941.pdf [firstpage_image] =>[orig_patent_app_number] => 12235815 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/235815
USB matrix switch system Sep 22, 2008 Issued
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