
S. Clardy
Examiner (ID: 19115)
| Most Active Art Unit | 1616 |
| Art Unit(s) | 2899, 1617, 1621, 1209, 1616 |
| Total Applications | 1393 |
| Issued Applications | 996 |
| Pending Applications | 126 |
| Abandoned Applications | 271 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4096038
[patent_doc_number] => 06163499
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Programmable impedance output buffer drivers, semiconductor devices and static random access memories provided with a programmable impedance output port'
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[patent_app_number] => 9/461117
[patent_app_country] => US
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Array
(
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[patent_doc_number] => 06178109
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[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Integrated circuit memory devices having reduced susceptibility to reference voltage signal noise'
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Array
(
[id] => 4369179
[patent_doc_number] => 06169689
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[patent_issue_date] => 2001-01-02
[patent_title] => 'MTJ stacked cell memory sensing method and apparatus'
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Array
(
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[patent_issue_date] => 2000-10-24
[patent_title] => 'Method for in-system programming of serially configured EEPROMS using a JTAG interface of a field programmable gate array'
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[patent_app_number] => 9/452017
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Array
(
[id] => 4165835
[patent_doc_number] => 06125068
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[patent_issue_date] => 2000-09-26
[patent_title] => 'Memory access control'
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Array
(
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[patent_issue_date] => 2000-10-31
[patent_title] => 'Low cost mixed memory integration with substantially coplanar gate surfaces'
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Array
(
[id] => 4420139
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/443623 | Electronic devices and low-voltage detection method | Nov 18, 1999 | Issued |
Array
(
[id] => 4407143
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[patent_issue_date] => 2001-10-02
[patent_title] => 'Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit'
[patent_app_type] => 1
[patent_app_number] => 9/440721
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[patent_app_date] => 1999-11-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/440721 | Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit | Nov 14, 1999 | Issued |
Array
(
[id] => 4202054
[patent_doc_number] => 06154384
[patent_country] => US
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[patent_issue_date] => 2000-11-28
[patent_title] => 'Ternary content addressable memory cell'
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Array
(
[id] => 4140215
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[patent_issue_date] => 2000-10-03
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[patent_app_type] => 1
[patent_app_number] => 9/438823
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Array
(
[id] => 4317187
[patent_doc_number] => 06188629
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[patent_title] => 'Low power, static content addressable memory'
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Array
(
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[patent_doc_number] => 06125061
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Array
(
[id] => 4309161
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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