Search

S. Clardy

Examiner (ID: 19115)

Most Active Art Unit
1616
Art Unit(s)
2899, 1617, 1621, 1209, 1616
Total Applications
1393
Issued Applications
996
Pending Applications
126
Abandoned Applications
271

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4096038 [patent_doc_number] => 06163499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Programmable impedance output buffer drivers, semiconductor devices and static random access memories provided with a programmable impedance output port' [patent_app_type] => 1 [patent_app_number] => 9/461117 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 6854 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163499.pdf [firstpage_image] =>[orig_patent_app_number] => 461117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461117
Programmable impedance output buffer drivers, semiconductor devices and static random access memories provided with a programmable impedance output port Dec 13, 1999 Issued
Array ( [id] => 4425518 [patent_doc_number] => 06178109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Integrated circuit memory devices having reduced susceptibility to reference voltage signal noise' [patent_app_type] => 1 [patent_app_number] => 9/457511 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3627 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178109.pdf [firstpage_image] =>[orig_patent_app_number] => 457511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457511
Integrated circuit memory devices having reduced susceptibility to reference voltage signal noise Dec 7, 1999 Issued
Array ( [id] => 4369179 [patent_doc_number] => 06169689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'MTJ stacked cell memory sensing method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/456615 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169689.pdf [firstpage_image] =>[orig_patent_app_number] => 456615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456615
MTJ stacked cell memory sensing method and apparatus Dec 7, 1999 Issued
Array ( [id] => 4261898 [patent_doc_number] => 06137738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method for in-system programming of serially configured EEPROMS using a JTAG interface of a field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 9/452017 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1764 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137738.pdf [firstpage_image] =>[orig_patent_app_number] => 452017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452017
Method for in-system programming of serially configured EEPROMS using a JTAG interface of a field programmable gate array Nov 29, 1999 Issued
Array ( [id] => 4165835 [patent_doc_number] => 06125068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Memory access control' [patent_app_type] => 1 [patent_app_number] => 9/450017 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1435 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125068.pdf [firstpage_image] =>[orig_patent_app_number] => 450017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/450017
Memory access control Nov 28, 1999 Issued
Array ( [id] => 4185115 [patent_doc_number] => 06141242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Low cost mixed memory integration with substantially coplanar gate surfaces' [patent_app_type] => 1 [patent_app_number] => 9/447629 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 39 [patent_no_of_words] => 8625 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141242.pdf [firstpage_image] =>[orig_patent_app_number] => 447629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447629
Low cost mixed memory integration with substantially coplanar gate surfaces Nov 22, 1999 Issued
Array ( [id] => 4420139 [patent_doc_number] => 06229751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Electronic devices and low-voltage detection method' [patent_app_type] => 1 [patent_app_number] => 9/443623 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3604 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229751.pdf [firstpage_image] =>[orig_patent_app_number] => 443623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/443623
Electronic devices and low-voltage detection method Nov 18, 1999 Issued
Array ( [id] => 4407143 [patent_doc_number] => 06297995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit' [patent_app_type] => 1 [patent_app_number] => 9/440721 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2028 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297995.pdf [firstpage_image] =>[orig_patent_app_number] => 440721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440721
Circuit configuration with a temperature-dependent semiconductor component test and repair logic circuit Nov 14, 1999 Issued
Array ( [id] => 4202054 [patent_doc_number] => 06154384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Ternary content addressable memory cell' [patent_app_type] => 1 [patent_app_number] => 9/439317 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2826 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154384.pdf [firstpage_image] =>[orig_patent_app_number] => 439317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439317
Ternary content addressable memory cell Nov 11, 1999 Issued
Array ( [id] => 4140215 [patent_doc_number] => 06128228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Circuit for high-precision analog reading of nonvolatile memory cells, in particular analog or multilevel flash or EEPROM memory cells' [patent_app_type] => 1 [patent_app_number] => 9/438823 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128228.pdf [firstpage_image] =>[orig_patent_app_number] => 438823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438823
Circuit for high-precision analog reading of nonvolatile memory cells, in particular analog or multilevel flash or EEPROM memory cells Nov 11, 1999 Issued
Array ( [id] => 4317187 [patent_doc_number] => 06188629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Low power, static content addressable memory' [patent_app_type] => 1 [patent_app_number] => 9/434713 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3664 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188629.pdf [firstpage_image] =>[orig_patent_app_number] => 434713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434713
Low power, static content addressable memory Nov 4, 1999 Issued
Array ( [id] => 4165729 [patent_doc_number] => 06125061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Semiconductor devices with built-in flash memory capable of easily increasing memory capacity by interconnecting them, and storage device provided with semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/433713 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4984 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125061.pdf [firstpage_image] =>[orig_patent_app_number] => 433713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433713
Semiconductor devices with built-in flash memory capable of easily increasing memory capacity by interconnecting them, and storage device provided with semiconductor device Nov 3, 1999 Issued
Array ( [id] => 4309161 [patent_doc_number] => 06198665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation' [patent_app_type] => 1 [patent_app_number] => 9/428925 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 41 [patent_no_of_words] => 10868 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198665.pdf [firstpage_image] =>[orig_patent_app_number] => 428925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/428925
One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation Oct 27, 1999 Issued
Array ( [id] => 4131506 [patent_doc_number] => 06072745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method for operating a memory' [patent_app_type] => 1 [patent_app_number] => 9/418111 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5943 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072745.pdf [firstpage_image] =>[orig_patent_app_number] => 418111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418111
Method for operating a memory Oct 13, 1999 Issued
Array ( [id] => 4384452 [patent_doc_number] => 06288955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Methods and systems for testing integrated circuit memory devices by overlappiing test result loading and test result analysis' [patent_app_type] => 1 [patent_app_number] => 9/415523 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288955.pdf [firstpage_image] =>[orig_patent_app_number] => 415523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415523
Methods and systems for testing integrated circuit memory devices by overlappiing test result loading and test result analysis Oct 7, 1999 Issued
Array ( [id] => 4231563 [patent_doc_number] => 06088280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'High-speed memory arranged for operating synchronously with a microprocessor' [patent_app_type] => 1 [patent_app_number] => 9/413928 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 8766 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088280.pdf [firstpage_image] =>[orig_patent_app_number] => 413928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413928
High-speed memory arranged for operating synchronously with a microprocessor Oct 6, 1999 Issued
Array ( [id] => 4284834 [patent_doc_number] => 06246613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell' [patent_app_type] => 1 [patent_app_number] => 9/411315 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11389 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246613.pdf [firstpage_image] =>[orig_patent_app_number] => 411315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411315
Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Oct 3, 1999 Issued
Array ( [id] => 4309348 [patent_doc_number] => 06198679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/408717 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 7030 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198679.pdf [firstpage_image] =>[orig_patent_app_number] => 408717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408717
Semiconductor memory device Sep 28, 1999 Issued
Array ( [id] => 4372602 [patent_doc_number] => 06191995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Sharing signal lines in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/386101 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4678 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191995.pdf [firstpage_image] =>[orig_patent_app_number] => 386101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386101
Sharing signal lines in a memory device Aug 29, 1999 Issued
Array ( [id] => 4394034 [patent_doc_number] => 06295245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Write data input circuit' [patent_app_type] => 1 [patent_app_number] => 9/385004 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7275 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295245.pdf [firstpage_image] =>[orig_patent_app_number] => 385004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385004
Write data input circuit Aug 26, 1999 Issued
Menu