S. Clardy

Array ( [id] => 4185872 [patent_doc_number] => 06141292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Clock generating circuits that utilize analog pump signals to provide fast synchronization and reduced delay skew' [patent_app_type] => 1 [patent_app_number] => 9/383805 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3693 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141292.pdf [firstpage_image] =>[orig_patent_app_number] => 383805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305248 [patent_doc_number] => 06236608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Technique to improve the source leakage of flash EPROM cells during source erase' [patent_app_type] => 1 [patent_app_number] => 9/375702 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5969 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236608.pdf [firstpage_image] =>[orig_patent_app_number] => 375702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305030 [patent_doc_number] => 06236592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Floating gate MOS transistor charge injection circuit and computation devices incorporating it' [patent_app_type] => 1 [patent_app_number] => 9/373813 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3079 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236592.pdf [firstpage_image] =>[orig_patent_app_number] => 373813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170248 [patent_doc_number] => 06108263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Memory system, method for verifying data stored in a memory system after a write cycle and method for writing to a memory system' [patent_app_type] => 1 [patent_app_number] => 9/373305 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108263.pdf [firstpage_image] =>[orig_patent_app_number] => 373305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4169933 [patent_doc_number] => 06108242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Flash memory with split gate structure and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/371702 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2794 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108242.pdf [firstpage_image] =>[orig_patent_app_number] => 371702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197121 [patent_doc_number] => 06160744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Semiconductor memory device and defect remedying method thereof' [patent_app_type] => 1 [patent_app_number] => 9/361203 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 117 [patent_figures_cnt] => 164 [patent_no_of_words] => 50489 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160744.pdf [firstpage_image] =>[orig_patent_app_number] => 361203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309133 [patent_doc_number] => 06198663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Non-volatile semiconductor memory IC' [patent_app_type] => 1 [patent_app_number] => 9/361904 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4033 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198663.pdf [firstpage_image] =>[orig_patent_app_number] => 361904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252531 [patent_doc_number] => 06166984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Non-volatile counter' [patent_app_type] => 1 [patent_app_number] => 9/360404 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3567 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166984.pdf [firstpage_image] =>[orig_patent_app_number] => 360404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4266133 [patent_doc_number] => 06208569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method of and apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/356805 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4638 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208569.pdf [firstpage_image] =>[orig_patent_app_number] => 356805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4095891 [patent_doc_number] => 06163489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Semiconductor memory having multiple redundant columns with offset segmentation boundaries' [patent_app_type] => 1 [patent_app_number] => 9/354304 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5788 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163489.pdf [firstpage_image] =>[orig_patent_app_number] => 354304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4393814 [patent_doc_number] => 06295231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'High-speed cycle clock-synchronous memory device' [patent_app_type] => 1 [patent_app_number] => 9/354102 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 11691 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295231.pdf [firstpage_image] =>[orig_patent_app_number] => 354102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247479 [patent_doc_number] => 06118717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method and apparatus for loading directly onto bit lines in a dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/354401 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 9 [patent_no_of_words] => 6502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118717.pdf [firstpage_image] =>[orig_patent_app_number] => 354401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170262 [patent_doc_number] => 06104650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Sacrifice read test mode' [patent_app_type] => 1 [patent_app_number] => 9/350602 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8114 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104650.pdf [firstpage_image] =>[orig_patent_app_number] => 350602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250625 [patent_doc_number] => 06144598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and apparatus for efficiently testing rambus memory devices' [patent_app_type] => 1 [patent_app_number] => 9/351105 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6229 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144598.pdf [firstpage_image] =>[orig_patent_app_number] => 351105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4169909 [patent_doc_number] => 06108241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Leakage detection in flash memory cell' [patent_app_type] => 1 [patent_app_number] => 9/345905 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6002 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108241.pdf [firstpage_image] =>[orig_patent_app_number] => 345905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309496 [patent_doc_number] => 06185119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Analog memory IC with fully differential signal path' [patent_app_type] => 1 [patent_app_number] => 9/345102 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 54 [patent_no_of_words] => 18832 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185119.pdf [firstpage_image] =>[orig_patent_app_number] => 345102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4230667 [patent_doc_number] => 06041005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/342105 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2640 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041005.pdf [firstpage_image] =>[orig_patent_app_number] => 342105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4116475 [patent_doc_number] => 06023427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Voltage pump switch' [patent_app_type] => 1 [patent_app_number] => 9/328285 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8362 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023427.pdf [firstpage_image] =>[orig_patent_app_number] => 328285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4116659 [patent_doc_number] => 06023440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook' [patent_app_type] => 1 [patent_app_number] => 9/320577 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 15939 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023440.pdf [firstpage_image] =>[orig_patent_app_number] => 320577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425598 [patent_doc_number] => 06195295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Segmented column memory device voltage steering technique' [patent_app_type] => 1 [patent_app_number] => 9/318895 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5472 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195295.pdf [firstpage_image] =>[orig_patent_app_number] => 318895 [rel_patent_id] =>[rel_patent_doc_number] =>)