Search

Sahana S. Kaup

Examiner (ID: 7980, Phone: (571)272-6897 , Office: P/1639 )

Most Active Art Unit
1639
Art Unit(s)
1675, 1639, 1612, 1684
Total Applications
558
Issued Applications
223
Pending Applications
64
Abandoned Applications
281

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16987976 [patent_doc_number] => 11075159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Integrated fan-out packages and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/035723 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035723 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035723
Integrated fan-out packages and methods of forming the same Jul 15, 2018 Issued
Array ( [id] => 18277083 [patent_doc_number] => 11616031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Semiconductor device and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/632665 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 69 [patent_no_of_words] => 45033 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16632665 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/632665
Semiconductor device and electronic apparatus Jul 12, 2018 Issued
Array ( [id] => 14657047 [patent_doc_number] => 20190235652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => MANUFACTURING METHOD FOR DISPLAY PANEL, SYSTEM FOR MANUFACTURING DISPLAY PANEL AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/033213 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033213 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033213
Manufacturing method for display panel, system for manufacturing display panel and display panel Jul 11, 2018 Issued
Array ( [id] => 13996525 [patent_doc_number] => 20190067420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/027825 [patent_app_country] => US [patent_app_date] => 2018-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16027825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/027825
Semiconductor device Jul 4, 2018 Issued
Array ( [id] => 15823121 [patent_doc_number] => 10636756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Semiconductor device and method of forming protrusion E-bar for 3D SIP [patent_app_type] => utility [patent_app_number] => 16/027731 [patent_app_country] => US [patent_app_date] => 2018-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 42 [patent_no_of_words] => 5293 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16027731 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/027731
Semiconductor device and method of forming protrusion E-bar for 3D SIP Jul 4, 2018 Issued
Array ( [id] => 14904335 [patent_doc_number] => 20190295933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/027442 [patent_app_country] => US [patent_app_date] => 2018-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16027442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/027442
Semiconductor device Jul 4, 2018 Issued
Array ( [id] => 16858371 [patent_doc_number] => 20210159116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => TREATING A SILICON ON INSULATOR WAFER IN PREPARATION FOR MANUFACTURING AN ATOMISTIC ELECTRONIC DEVICE INTERFACED WITH A CMOS ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/632460 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16632460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/632460
Treating a silicon on insulator wafer in preparation for manufacturing an atomistic electronic device interfaced with a CMOS electronic device Jun 28, 2018 Issued
Array ( [id] => 17730930 [patent_doc_number] => 11387332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/981582 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3215 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16981582 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/981582
Method for manufacturing semiconductor device Jun 26, 2018 Issued
Array ( [id] => 16339404 [patent_doc_number] => 10790374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Method for forming ohmic contacts [patent_app_type] => utility [patent_app_number] => 16/017145 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 3512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017145 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017145
Method for forming ohmic contacts Jun 24, 2018 Issued
Array ( [id] => 13499747 [patent_doc_number] => 20180301416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => COPPER ETCHING INTEGRATION SCHEME [patent_app_type] => utility [patent_app_number] => 16/017039 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017039
Copper etching integration scheme Jun 24, 2018 Issued
Array ( [id] => 13629683 [patent_doc_number] => 20180366394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => IMPLANT DEVICE AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/008532 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008532 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008532
IMPLANT DEVICE AND METHOD OF MAKING THE SAME Jun 13, 2018 Abandoned
Array ( [id] => 16653329 [patent_doc_number] => 10930522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Semiconductor layer, oscillation element, and semiconductor layer manufacturing method [patent_app_type] => utility [patent_app_number] => 16/620221 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 14909 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16620221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/620221
Semiconductor layer, oscillation element, and semiconductor layer manufacturing method Jun 7, 2018 Issued
Array ( [id] => 13471017 [patent_doc_number] => 20180287051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => BOTTOM ELECTRODE FOR MRAM APPLICATIONS [patent_app_type] => utility [patent_app_number] => 15/997904 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997904 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/997904
Bottom electrode for MRAM applications Jun 4, 2018 Issued
Array ( [id] => 14301003 [patent_doc_number] => 10290633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => CMOS compatible fuse or resistor using self-aligned contacts [patent_app_type] => utility [patent_app_number] => 15/997154 [patent_app_country] => US [patent_app_date] => 2018-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997154 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/997154
CMOS compatible fuse or resistor using self-aligned contacts Jun 3, 2018 Issued
Array ( [id] => 13598789 [patent_doc_number] => 20180350943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/997307 [patent_app_country] => US [patent_app_date] => 2018-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 520 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/997307
Method for manufacturing a semiconductor device Jun 3, 2018 Issued
Array ( [id] => 16410193 [patent_doc_number] => 10818762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Gate contact over active region in cell [patent_app_type] => utility [patent_app_number] => 15/989604 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989604 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989604
Gate contact over active region in cell May 24, 2018 Issued
Array ( [id] => 13452201 [patent_doc_number] => 20180277643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR [patent_app_type] => utility [patent_app_number] => 15/989977 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989977 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989977
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR May 24, 2018 Abandoned
Array ( [id] => 14317607 [patent_doc_number] => 20190148507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => TRANSISTOR LAYOUT TO REDUCE KINK EFFECT [patent_app_type] => utility [patent_app_number] => 15/989606 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989606
Transistor layout to reduce kink effect May 24, 2018 Issued
Array ( [id] => 15791721 [patent_doc_number] => 10629592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Through silicon via design for stacking integrated circuits [patent_app_type] => utility [patent_app_number] => 15/989556 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 7683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989556 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989556
Through silicon via design for stacking integrated circuits May 24, 2018 Issued
Array ( [id] => 15077821 [patent_doc_number] => 10468410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Metal gate modulation to improve kink effect [patent_app_type] => utility [patent_app_number] => 15/989648 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 50 [patent_no_of_words] => 11205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989648 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989648
Metal gate modulation to improve kink effect May 24, 2018 Issued
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