Search

Sahana S. Kaup

Examiner (ID: 7980, Phone: (571)272-6897 , Office: P/1639 )

Most Active Art Unit
1639
Art Unit(s)
1675, 1639, 1612, 1684
Total Applications
558
Issued Applications
223
Pending Applications
64
Abandoned Applications
281

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13500065 [patent_doc_number] => 20180301575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => COMPOUND SEMICONDUCTOR SOLAR CELL AND METHOD FOR MANUFACTURING A FRONT ELECTRODE OF THE SOLAR CELL [patent_app_type] => utility [patent_app_number] => 15/948231 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948231 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948231
COMPOUND SEMICONDUCTOR SOLAR CELL AND METHOD FOR MANUFACTURING A FRONT ELECTRODE OF THE SOLAR CELL Apr 8, 2018 Abandoned
Array ( [id] => 16752687 [patent_doc_number] => 20210104699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => ORGANIC EL DEVICE SUBSTRATE, ORGANIC EL DEVICE, AND METHOD FOR MANUFACTURING ORGANIC EL DEVICE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/608327 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16608327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/608327
ORGANIC EL DEVICE SUBSTRATE, ORGANIC EL DEVICE, AND METHOD FOR MANUFACTURING ORGANIC EL DEVICE SUBSTRATE Apr 3, 2018 Abandoned
Array ( [id] => 17254096 [patent_doc_number] => 11189594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Bonding apparatus and bonding method [patent_app_type] => utility [patent_app_number] => 16/499869 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 10048 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16499869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/499869
Bonding apparatus and bonding method Mar 21, 2018 Issued
Array ( [id] => 17221908 [patent_doc_number] => 11174399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Surface treatment method for imparting alcohol repellency to semiconductor substrate [patent_app_type] => utility [patent_app_number] => 16/615920 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4754 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16615920 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/615920
Surface treatment method for imparting alcohol repellency to semiconductor substrate Mar 15, 2018 Issued
Array ( [id] => 13420111 [patent_doc_number] => 20180261598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => LOW RESISTANCE SOURCE/DRAIN CONTACTS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES [patent_app_type] => utility [patent_app_number] => 15/914096 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914096 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914096
Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices Mar 6, 2018 Issued
Array ( [id] => 15250293 [patent_doc_number] => 10510675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Substrate structure with spatial arrangement configured for coupling of surface plasmons to incident light [patent_app_type] => utility [patent_app_number] => 15/888366 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8661 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888366 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/888366
Substrate structure with spatial arrangement configured for coupling of surface plasmons to incident light Feb 4, 2018 Issued
Array ( [id] => 12760243 [patent_doc_number] => 20180145249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => IMPLEMENTING DEPOSITION GROWTH METHOD FOR MAGNETIC MEMORY [patent_app_type] => utility [patent_app_number] => 15/876632 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876632
Implementing deposition growth method for magnetic memory Jan 21, 2018 Issued
Array ( [id] => 13320665 [patent_doc_number] => 20180211870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/875442 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875442 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875442
Interconnect structure and method of forming the same Jan 18, 2018 Issued
Array ( [id] => 14631487 [patent_doc_number] => 20190229113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => ISOLATION ENHANCEMENT WITH ON-DIE SLOT-LINE ON POWER/GROUND GRID STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/875568 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875568 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875568
Isolation enhancement with on-die slot-line on power/ground grid structure Jan 18, 2018 Issued
Array ( [id] => 15308689 [patent_doc_number] => 10519034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Semiconductor device and method of producing a semiconductor device [patent_app_type] => utility [patent_app_number] => 15/875635 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9567 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875635
Semiconductor device and method of producing a semiconductor device Jan 18, 2018 Issued
Array ( [id] => 14268103 [patent_doc_number] => 10283624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-07 [patent_title] => Semiconductor structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 15/875485 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875485 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875485
Semiconductor structure and method for forming the same Jan 18, 2018 Issued
Array ( [id] => 13099325 [patent_doc_number] => 10069009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Method for forming recess within epitaxial layer [patent_app_type] => utility [patent_app_number] => 15/861700 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4113 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15861700 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/861700
Method for forming recess within epitaxial layer Jan 3, 2018 Issued
Array ( [id] => 12918478 [patent_doc_number] => 20180198002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => METHOD FOR MANUFACTURING SOLAR CELL [patent_app_type] => utility [patent_app_number] => 15/857242 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15857242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/857242
Method for manufacturing solar cell Dec 27, 2017 Issued
Array ( [id] => 13594033 [patent_doc_number] => 20180348565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/848940 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848940
DISPLAY PANEL AND MANUFACTURING METHOD THEREOF Dec 19, 2017 Abandoned
Array ( [id] => 12849979 [patent_doc_number] => 20180175166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERNAL SPACERS [patent_app_type] => utility [patent_app_number] => 15/837217 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837217
Method for producing a semiconductor device with self-aligned internal spacers Dec 10, 2017 Issued
Array ( [id] => 14920711 [patent_doc_number] => 10431683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Method for making a semiconductor device with a compressive stressed channel [patent_app_type] => utility [patent_app_number] => 15/837281 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 7322 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837281
Method for making a semiconductor device with a compressive stressed channel Dec 10, 2017 Issued
Array ( [id] => 12803080 [patent_doc_number] => 20180159530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => Tuning Capacitance to Enhance FET Stack Voltage Withstand [patent_app_type] => utility [patent_app_number] => 15/829773 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829773 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/829773
Tuning capacitance to enhance FET stack voltage withstand Nov 30, 2017 Issued
Array ( [id] => 14955159 [patent_doc_number] => 10438858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Low-cost SOI FinFET technology [patent_app_type] => utility [patent_app_number] => 15/827195 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5220 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15827195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/827195
Low-cost SOI FinFET technology Nov 29, 2017 Issued
Array ( [id] => 16981828 [patent_doc_number] => 20210226065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => THIN FILM TRANSISTOR AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/099506 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16099506 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/099506
Thin film transistor and display apparatus Nov 21, 2017 Issued
Array ( [id] => 13945233 [patent_doc_number] => 10208379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Synthesis and use of precursors for ALD of group VA element containing thin films [patent_app_type] => utility [patent_app_number] => 15/820188 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 24374 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820188 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820188
Synthesis and use of precursors for ALD of group VA element containing thin films Nov 20, 2017 Issued
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