
Sahana S. Kaup
Examiner (ID: 7980, Phone: (571)272-6897 , Office: P/1639 )
| Most Active Art Unit | 1639 |
| Art Unit(s) | 1675, 1639, 1612, 1684 |
| Total Applications | 558 |
| Issued Applications | 223 |
| Pending Applications | 64 |
| Abandoned Applications | 281 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13159697
[patent_doc_number] => 10096584
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-09
[patent_title] => Method for producing a power semiconductor module
[patent_app_type] => utility
[patent_app_number] => 15/337733
[patent_app_country] => US
[patent_app_date] => 2016-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 4386
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15337733
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/337733 | Method for producing a power semiconductor module | Oct 27, 2016 | Issued |
Array
(
[id] => 11446208
[patent_doc_number] => 20170047229
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-16
[patent_title] => 'STACK FRAME FOR ELECTRICAL CONNECTIONS AND THE METHOD TO FABRICATE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/334307
[patent_app_country] => US
[patent_app_date] => 2016-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 5652
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15334307
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/334307 | Stack frame for electrical connections and the method to fabricate thereof | Oct 25, 2016 | Issued |
Array
(
[id] => 13099035
[patent_doc_number] => 10068863
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-04
[patent_title] => Formation of solder and copper interconnect structures and associated techniques and configurations
[patent_app_type] => utility
[patent_app_number] => 15/293103
[patent_app_country] => US
[patent_app_date] => 2016-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 11239
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293103
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/293103 | Formation of solder and copper interconnect structures and associated techniques and configurations | Oct 12, 2016 | Issued |
Array
(
[id] => 12195485
[patent_doc_number] => 09899220
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-20
[patent_title] => 'Method for patterning a substrate involving directed self-assembly'
[patent_app_type] => utility
[patent_app_number] => 15/289550
[patent_app_country] => US
[patent_app_date] => 2016-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 43
[patent_no_of_words] => 4902
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289550
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/289550 | Method for patterning a substrate involving directed self-assembly | Oct 9, 2016 | Issued |
Array
(
[id] => 11608264
[patent_doc_number] => 20170125568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/289534
[patent_app_country] => US
[patent_app_date] => 2016-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 8935
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289534
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/289534 | Compound semiconductor device and method of manufacturing the same | Oct 9, 2016 | Issued |
Array
(
[id] => 13019521
[patent_doc_number] => 10032880
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-24
[patent_title] => Method for forming ohmic contacts
[patent_app_type] => utility
[patent_app_number] => 15/289519
[patent_app_country] => US
[patent_app_date] => 2016-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 23
[patent_no_of_words] => 3466
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289519
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/289519 | Method for forming ohmic contacts | Oct 9, 2016 | Issued |
Array
(
[id] => 11623037
[patent_doc_number] => 20170133224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-11
[patent_title] => 'INTEGRATED PROCESS AND STRUCTURE TO FORM III-V CHANNEL FOR SUB-7NM CMOS DEVICES'
[patent_app_type] => utility
[patent_app_number] => 15/277394
[patent_app_country] => US
[patent_app_date] => 2016-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3388
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277394
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/277394 | Integrated process and structure to form III-V channel for sub-7nm CMOS devices | Sep 26, 2016 | Issued |
Array
(
[id] => 11898123
[patent_doc_number] => 09768062
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-09-19
[patent_title] => 'Method for forming low parasitic capacitance source and drain contacts'
[patent_app_type] => utility
[patent_app_number] => 15/276748
[patent_app_country] => US
[patent_app_date] => 2016-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 9467
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276748
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/276748 | Method for forming low parasitic capacitance source and drain contacts | Sep 25, 2016 | Issued |
Array
(
[id] => 12061984
[patent_doc_number] => 20170338328
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'METHOD OF FORMING INTERNAL DIELECTRIC SPACERS FOR HORIZONTAL NANOSHEET FET ARCHITECTURES'
[patent_app_type] => utility
[patent_app_number] => 15/276784
[patent_app_country] => US
[patent_app_date] => 2016-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6155
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276784
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/276784 | Method of forming internal dielectric spacers for horizontal nanosheet FET architectures | Sep 25, 2016 | Issued |
Array
(
[id] => 11623040
[patent_doc_number] => 20170133227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-11
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/276722
[patent_app_country] => US
[patent_app_date] => 2016-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8239
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276722
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/276722 | Method of manufacturing semiconductor device | Sep 25, 2016 | Issued |
Array
(
[id] => 11386071
[patent_doc_number] => 20170012127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-12
[patent_title] => 'SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS'
[patent_app_type] => utility
[patent_app_number] => 15/255862
[patent_app_country] => US
[patent_app_date] => 2016-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3915
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15255862
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/255862 | Semiconductor device with fin and related methods | Sep 1, 2016 | Issued |
Array
(
[id] => 11539579
[patent_doc_number] => 09613996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-04
[patent_title] => 'Backside structure and methods for BSI image sensors'
[patent_app_type] => utility
[patent_app_number] => 15/218266
[patent_app_country] => US
[patent_app_date] => 2016-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8230
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15218266
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/218266 | Backside structure and methods for BSI image sensors | Jul 24, 2016 | Issued |
Array
(
[id] => 15110517
[patent_doc_number] => 10476598
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-11-12
[patent_title] => Optical communication circuits
[patent_app_type] => utility
[patent_app_number] => 15/219005
[patent_app_country] => US
[patent_app_date] => 2016-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4341
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219005
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/219005 | Optical communication circuits | Jul 24, 2016 | Issued |
Array
(
[id] => 11353885
[patent_doc_number] => 20160372625
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-22
[patent_title] => 'ADVANCED HYDROGENATION OF SILICON SOLAR CELLS'
[patent_app_type] => utility
[patent_app_number] => 15/204813
[patent_app_country] => US
[patent_app_date] => 2016-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 20619
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15204813
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/204813 | Advanced hydrogenation of silicon solar cells | Jul 6, 2016 | Issued |
Array
(
[id] => 12195856
[patent_doc_number] => 09899595
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-20
[patent_title] => 'Implementing deposition growth method for magnetic memory'
[patent_app_type] => utility
[patent_app_number] => 15/197847
[patent_app_country] => US
[patent_app_date] => 2016-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 52
[patent_no_of_words] => 6403
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15197847
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/197847 | Implementing deposition growth method for magnetic memory | Jun 29, 2016 | Issued |
Array
(
[id] => 11110907
[patent_doc_number] => 20160307877
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-20
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/193875
[patent_app_country] => US
[patent_app_date] => 2016-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 14134
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193875
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/193875 | Semiconductor device and manufacturing method of the same | Jun 26, 2016 | Issued |
Array
(
[id] => 12849031
[patent_doc_number] => 20180174850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE ELECTRODE
[patent_app_type] => utility
[patent_app_number] => 15/574942
[patent_app_country] => US
[patent_app_date] => 2016-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2363
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574942
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/574942 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE ELECTRODE | Jun 20, 2016 | Abandoned |
Array
(
[id] => 11087809
[patent_doc_number] => 20160284777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-29
[patent_title] => 'ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY'
[patent_app_type] => utility
[patent_app_number] => 15/178348
[patent_app_country] => US
[patent_app_date] => 2016-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 12111
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178348
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/178348 | Organic light-emitting diode (OLED) display | Jun 8, 2016 | Issued |
Array
(
[id] => 11475630
[patent_doc_number] => 20170062413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-02
[patent_title] => 'CMOS COMPATIBLE FUSE OR RESISTOR USING SELF-ALIGNED CONTACTS'
[patent_app_type] => utility
[patent_app_number] => 15/176258
[patent_app_country] => US
[patent_app_date] => 2016-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4266
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176258
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/176258 | CMOS compatible fuse or resistor using self-aligned contacts | Jun 7, 2016 | Issued |
Array
(
[id] => 14046007
[patent_doc_number] => 20190079110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-14
[patent_title] => MEMS DEVICE AND ELECTRONIC APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/078213
[patent_app_country] => US
[patent_app_date] => 2016-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2382
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 29
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16078213
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/078213 | MEMS device and electronic apparatus | Jun 1, 2016 | Issued |