| Application number | Title of the application | Filing Date | Status |
|---|
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[patent_issue_date] => 1999-01-19
[patent_title] => 'System and method for accessing and distributing electronic documents'
[patent_app_type] => 1
[patent_app_number] => 8/493376
[patent_app_country] => US
[patent_app_date] => 1995-06-21
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Array
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[patent_doc_number] => 05590295
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'System and method for register renaming'
[patent_app_type] => 1
[patent_app_number] => 8/478531
[patent_app_country] => US
[patent_app_date] => 1995-06-07
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[firstpage_image] =>[orig_patent_app_number] => 478531
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/478531 | System and method for register renaming | Jun 6, 1995 | Issued |
| 08/475416 | METHOD FOR EXECUTION OF PROGRAM STEPS BY A REMOTE CPU IN A COMPUTER NETWORK | Jun 6, 1995 | Abandoned |
Array
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[id] => 3616458
[patent_doc_number] => 05579496
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Method and apparatus for processing control instructions received from multiple sources connected to a communication bus'
[patent_app_type] => 1
[patent_app_number] => 8/483629
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 483629
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/483629 | Method and apparatus for processing control instructions received from multiple sources connected to a communication bus | Jun 6, 1995 | Issued |
| 08/483285 | MEHTOD AND APPARATUS FOR PERFORMING A STORE OPERATION | Jun 6, 1995 | Abandoned |
Array
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[patent_kind] => B1
[patent_issue_date] => 2003-08-05
[patent_title] => 'Data address prediction structure and a method for operating the same'
[patent_app_type] => B1
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Array
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[patent_doc_number] => 06484252
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[patent_title] => 'Microprocessor with improved instruction cycle using time-compressed fetching'
[patent_app_type] => B1
[patent_app_number] => 08/488082
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Array
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[patent_app_type] => 1
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Array
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[patent_country] => US
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[patent_issue_date] => 1997-07-01
[patent_title] => 'Integrated audio decoder system and method of operation'
[patent_app_type] => 1
[patent_app_number] => 8/475251
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 475251
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/475251 | Integrated audio decoder system and method of operation | Jun 6, 1995 | Issued |
Array
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[id] => 3674242
[patent_doc_number] => 05657454
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Audio decoder circuit and method of operation'
[patent_app_type] => 1
[patent_app_number] => 8/477028
[patent_app_country] => US
[patent_app_date] => 1995-06-07
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[firstpage_image] =>[orig_patent_app_number] => 477028
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/477028 | Audio decoder circuit and method of operation | Jun 6, 1995 | Issued |
Array
(
[id] => 3735889
[patent_doc_number] => 05673408
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-30
[patent_title] => 'Processor structure and method for renamable trap-stack'
[patent_app_type] => 1
[patent_app_number] => 8/472394
[patent_app_country] => US
[patent_app_date] => 1995-06-07
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[firstpage_image] =>[orig_patent_app_number] => 472394
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/472394 | Processor structure and method for renamable trap-stack | Jun 6, 1995 | Issued |
| 08/473514 | METHOD AND APPARATUS FOR SORTING INCOMING INTERLEAVED ASYNCHRONOUS TRANSFER MODE CELLS | Jun 6, 1995 | Abandoned |
Array
(
[id] => 3564176
[patent_doc_number] => 05572690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Cascaded multistage counterflow pipeline processor for carrying distinct data in two opposite directions'
[patent_app_type] => 1
[patent_app_number] => 8/468884
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Array
(
[id] => 3705729
[patent_doc_number] => 05651123
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'Program execution control device having addressability in accordance with M series pseudo-random number sequence'
[patent_app_type] => 1
[patent_app_number] => 8/460947
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/460947 | Program execution control device having addressability in accordance with M series pseudo-random number sequence | Jun 4, 1995 | Issued |
| 08/456746 | PROGRAMMABLE INSTRUCTION TRAP SYSTEM AND METHOD | May 31, 1995 | Abandoned |
| 08/457049 | METHOD AND APPARATUS FOR ROTATING ACTIVE INSTRUCTIONS IN A PARALLEL DATA PROCESSOR | May 31, 1995 | Abandoned |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Input buffer device for a printer using an FIFO and data input method'
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Array
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[id] => 3970827
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Digital network including early packet discard mechanism with adjustable threshold'
[patent_app_type] => 1
[patent_app_number] => 8/445673
[patent_app_country] => US
[patent_app_date] => 1995-05-22
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Array
(
[id] => 3933479
[patent_doc_number] => 05945994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Kinematic-simulation apparatus and kinematic-simulation method with interference processing'
[patent_app_type] => 1
[patent_app_number] => 8/444358
[patent_app_country] => US
[patent_app_date] => 1995-05-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/444358 | Kinematic-simulation apparatus and kinematic-simulation method with interference processing | May 17, 1995 | Issued |
| 08/441261 | STALLING AN INSTRUCTION PIPELINE DURING INSTRUCTION STREAM REPAIRS IN A PROCESSOR | May 14, 1995 | Abandoned |