Salvatore A Cangialosi

Array ( [id] => 5679350 [patent_doc_number] => 20060184706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link' [patent_app_type] => utility [patent_app_number] => 11/055847 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184706.pdf [firstpage_image] =>[orig_patent_app_number] => 11055847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7207182 [patent_doc_number] => 20050166098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'DSP bus monitoring apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/053446 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7191 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166098.pdf [firstpage_image] =>[orig_patent_app_number] => 11053446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 462132 [patent_doc_number] => 07246185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-17 [patent_title] => 'Master and slave side arbitrators associated with programmable chip system components' [patent_app_type] => utility [patent_app_number] => 11/049141 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5783 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/246/07246185.pdf [firstpage_image] =>[orig_patent_app_number] => 11049141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 381117 [patent_doc_number] => 07310696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-18 [patent_title] => 'Method and system for coordinating interoperability between devices of varying capabilities in a network' [patent_app_type] => utility [patent_app_number] => 11/044525 [patent_app_country] => US [patent_app_date] => 2005-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6212 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310696.pdf [firstpage_image] =>[orig_patent_app_number] => 11044525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7098000 [patent_doc_number] => 20050130459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Configurable connectorized I/O system' [patent_app_type] => utility [patent_app_number] => 11/043296 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5091 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130459.pdf [firstpage_image] =>[orig_patent_app_number] => 11043296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 472815 [patent_doc_number] => 07234018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-19 [patent_title] => 'Layered crossbar for interconnection of multiple processors and shared memories' [patent_app_type] => utility [patent_app_number] => 11/023969 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13076 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/234/07234018.pdf [firstpage_image] =>[orig_patent_app_number] => 11023969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 481193 [patent_doc_number] => 07228372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Data communication system with an SPI bus having a plurality of devices wherein data communications are enabled using communication protocols optimum to respective devices' [patent_app_type] => utility [patent_app_number] => 11/016769 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 6223 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228372.pdf [firstpage_image] =>[orig_patent_app_number] => 11016769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 535650 [patent_doc_number] => 07191256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Combined host interface controller for conducting communication between a host system and multiple devices in multiple protocols' [patent_app_type] => utility [patent_app_number] => 11/015295 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4080 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191256.pdf [firstpage_image] =>[orig_patent_app_number] => 11015295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5846855 [patent_doc_number] => 20060123181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Wireless USB hardware scheduling' [patent_app_type] => utility [patent_app_number] => 11/004429 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8030 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123181.pdf [firstpage_image] =>[orig_patent_app_number] => 11004429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7100229 [patent_doc_number] => 20050132105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Mobius time-triggered communication' [patent_app_type] => utility [patent_app_number] => 10/993923 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5593 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132105.pdf [firstpage_image] =>[orig_patent_app_number] => 10993923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5867056 [patent_doc_number] => 20060101187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Multi port processor architecture' [patent_app_type] => utility [patent_app_number] => 10/890346 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101187.pdf [firstpage_image] =>[orig_patent_app_number] => 10890346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7013415 [patent_doc_number] => 20050066099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Interrupt disabling apparatus, system, and method' [patent_app_type] => utility [patent_app_number] => 10/977204 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3858 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20050066099.pdf [firstpage_image] =>[orig_patent_app_number] => 10977204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7248205 [patent_doc_number] => 20050074020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Method and system for improved processing of CPU intensive communications protocols' [patent_app_type] => utility [patent_app_number] => 10/976139 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4601 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20050074020.pdf [firstpage_image] =>[orig_patent_app_number] => 10976139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 400495 [patent_doc_number] => 07296103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method and system for dynamically selecting wafer lots for metrology processing' [patent_app_type] => utility [patent_app_number] => 10/958834 [patent_app_country] => US [patent_app_date] => 2004-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6036 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/296/07296103.pdf [firstpage_image] =>[orig_patent_app_number] => 10958834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6985167 [patent_doc_number] => 20050154809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Method for configuring and/or operating an automation device' [patent_app_type] => utility [patent_app_number] => 10/957594 [patent_app_country] => US [patent_app_date] => 2004-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3131 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20050154809.pdf [firstpage_image] =>[orig_patent_app_number] => 10957594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7166676 [patent_doc_number] => 20050086403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'USB composite device and method using hub link layer and UTMI interface' [patent_app_type] => utility [patent_app_number] => 10/957652 [patent_app_country] => US [patent_app_date] => 2004-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2092 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086403.pdf [firstpage_image] =>[orig_patent_app_number] => 10957652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5722402 [patent_doc_number] => 20060075178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Communication between logical macros' [patent_app_type] => utility [patent_app_number] => 10/958967 [patent_app_country] => US [patent_app_date] => 2004-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2409 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20060075178.pdf [firstpage_image] =>[orig_patent_app_number] => 10958967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 469213 [patent_doc_number] => 07240134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Circuit with processing prevention unit' [patent_app_type] => utility [patent_app_number] => 10/958182 [patent_app_country] => US [patent_app_date] => 2004-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 9132 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240134.pdf [firstpage_image] =>[orig_patent_app_number] => 10958182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7166782 [patent_doc_number] => 20050086434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Multimedia/secure digital cards and adapters for interfacing to hosts and methods of operating' [patent_app_type] => utility [patent_app_number] => 10/957501 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4288 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086434.pdf [firstpage_image] =>[orig_patent_app_number] => 10957501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 561923 [patent_doc_number] => 07165132 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-16 [patent_title] => 'Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged' [patent_app_type] => utility [patent_app_number] => 10/956650 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3381 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/165/07165132.pdf [firstpage_image] =>[orig_patent_app_number] => 10956650 [rel_patent_id] =>[rel_patent_doc_number] =>)