![](/images/general/no_picture/200_user.png)
Salvatore A Cangialosi
Examiner (ID: 11118)
Most Active Art Unit | 2202 |
Art Unit(s) | 2304, 2746, 3305, 2766, 3642, 2661, 2200, 2201, 2202, 2732, 3402, 3621, 2899 |
Total Applications | 2208 |
Issued Applications | 1964 |
Pending Applications | 90 |
Abandoned Applications | 154 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 739486
[patent_doc_number] => 07039745
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-02
[patent_title] => 'Control system including controller and field devices'
[patent_app_type] => utility
[patent_app_number] => 10/831180
[patent_app_country] => US
[patent_app_date] => 2004-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6988
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/039/07039745.pdf
[firstpage_image] =>[orig_patent_app_number] => 10831180
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/831180 | Control system including controller and field devices | Apr 25, 2004 | Issued |
Array
(
[id] => 7321186
[patent_doc_number] => 20040225824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Network of computing devices including a repeater for distributed arbitration digital data buses'
[patent_app_type] => new
[patent_app_number] => 10/824072
[patent_app_country] => US
[patent_app_date] => 2004-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0225/20040225824.pdf
[firstpage_image] =>[orig_patent_app_number] => 10824072
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/824072 | Network of computing devices including a repeater for distributed arbitration digital data buses | Apr 12, 2004 | Abandoned |
Array
(
[id] => 908335
[patent_doc_number] => 07337258
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-02-26
[patent_title] => 'Dynamically allocating devices to buses'
[patent_app_type] => utility
[patent_app_number] => 10/823155
[patent_app_country] => US
[patent_app_date] => 2004-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3829
[patent_no_of_claims] => 11
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[pdf_file] => patents/07/337/07337258.pdf
[firstpage_image] =>[orig_patent_app_number] => 10823155
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/823155 | Dynamically allocating devices to buses | Apr 11, 2004 | Issued |
Array
(
[id] => 684622
[patent_doc_number] => 07085874
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits'
[patent_app_type] => utility
[patent_app_number] => 10/815980
[patent_app_country] => US
[patent_app_date] => 2004-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 5569
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/085/07085874.pdf
[firstpage_image] =>[orig_patent_app_number] => 10815980
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/815980 | Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits | Apr 1, 2004 | Issued |
Array
(
[id] => 6999491
[patent_doc_number] => 20050138246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'SERIAL/PARALLEL DATA TRANSFORMER MODULE AND RELATED COMPUTER SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 10/708947
[patent_app_country] => US
[patent_app_date] => 2004-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 3604
[patent_no_of_claims] => 29
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[pdf_file] => publications/A1/0138/20050138246.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708947
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708947 | SERIAL/PARALLEL DATA TRANSFORMER MODULE AND RELATED COMPUTER SYSTEM | Apr 1, 2004 | Abandoned |
Array
(
[id] => 524317
[patent_doc_number] => 07197588
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'Interrupt scheme for an Input/Output device'
[patent_app_type] => utility
[patent_app_number] => 10/816435
[patent_app_country] => US
[patent_app_date] => 2004-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 7781
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[pdf_file] => patents/07/197/07197588.pdf
[firstpage_image] =>[orig_patent_app_number] => 10816435
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/816435 | Interrupt scheme for an Input/Output device | Mar 30, 2004 | Issued |
Array
(
[id] => 6962071
[patent_doc_number] => 20050216638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'Virtual bus interface production of header-type fields from data-type fields'
[patent_app_type] => utility
[patent_app_number] => 10/812150
[patent_app_country] => US
[patent_app_date] => 2004-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 7075
[patent_no_of_claims] => 18
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[pdf_file] => publications/A1/0216/20050216638.pdf
[firstpage_image] =>[orig_patent_app_number] => 10812150
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/812150 | Virtual bus interface production of header-type fields from data-type fields | Mar 28, 2004 | Issued |
Array
(
[id] => 7196116
[patent_doc_number] => 20040205279
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Bus communication system by unrestrained connection and a communication control method therefor'
[patent_app_type] => new
[patent_app_number] => 10/808560
[patent_app_country] => US
[patent_app_date] => 2004-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 12516
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 88
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20040205279.pdf
[firstpage_image] =>[orig_patent_app_number] => 10808560
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/808560 | Bus communication system by unrestrained connection and a communication control method therefor | Mar 24, 2004 | Issued |
Array
(
[id] => 649004
[patent_doc_number] => 07120723
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-10
[patent_title] => 'System and method for memory hub-based expansion bus'
[patent_app_type] => utility
[patent_app_number] => 10/810229
[patent_app_country] => US
[patent_app_date] => 2004-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 5379
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[pdf_file] => patents/07/120/07120723.pdf
[firstpage_image] =>[orig_patent_app_number] => 10810229
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/810229 | System and method for memory hub-based expansion bus | Mar 24, 2004 | Issued |
Array
(
[id] => 6962109
[patent_doc_number] => 20050216647
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'Bus configuration multiplexer'
[patent_app_type] => utility
[patent_app_number] => 10/808881
[patent_app_country] => US
[patent_app_date] => 2004-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0216/20050216647.pdf
[firstpage_image] =>[orig_patent_app_number] => 10808881
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/808881 | Device bandwidth management using a bus configuration multiplexer | Mar 23, 2004 | Issued |
Array
(
[id] => 7112718
[patent_doc_number] => 20050210174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'System and method for forwarding interrupt requests'
[patent_app_type] => utility
[patent_app_number] => 10/804873
[patent_app_country] => US
[patent_app_date] => 2004-03-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0210/20050210174.pdf
[firstpage_image] =>[orig_patent_app_number] => 10804873
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/804873 | System and method for delaying an interrupt request until corresponding data is provided to a destination device | Mar 18, 2004 | Issued |
Array
(
[id] => 721544
[patent_doc_number] => 07054967
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-30
[patent_title] => 'SRAM bus architecture and interconnect to an FPGA'
[patent_app_type] => utility
[patent_app_number] => 10/802577
[patent_app_country] => US
[patent_app_date] => 2004-03-16
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[pdf_file] => patents/07/054/07054967.pdf
[firstpage_image] =>[orig_patent_app_number] => 10802577
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/802577 | SRAM bus architecture and interconnect to an FPGA | Mar 15, 2004 | Issued |
Array
(
[id] => 623193
[patent_doc_number] => 07143220
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[patent_title] => 'Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies'
[patent_app_type] => utility
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[pdf_file] => patents/07/143/07143220.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/797771 | Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies | Mar 9, 2004 | Issued |
Array
(
[id] => 7472143
[patent_doc_number] => 20040199701
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[patent_issue_date] => 2004-10-07
[patent_title] => 'Bus system and method for exchanging data'
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[patent_app_number] => 10/484141
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[firstpage_image] =>[orig_patent_app_number] => 10484141
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/484141 | Bus system and method for exchanging data | Mar 7, 2004 | Abandoned |
Array
(
[id] => 7277441
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[patent_title] => 'Method, system and device for a processor to access devices of different speeds using a standard memory bus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/793360 | Method, system and device for a processor to access devices of different speeds using a standard memory bus | Mar 2, 2004 | Issued |
Array
(
[id] => 465752
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[patent_issue_date] => 2007-07-10
[patent_title] => 'I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures'
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[pdf_file] => patents/07/243/07243175.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/792168 | I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures | Mar 1, 2004 | Issued |
Array
(
[id] => 695173
[patent_doc_number] => 07076585
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[patent_issue_date] => 2006-07-11
[patent_title] => 'System bus controller and the method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708274 | System bus controller and the method thereof | Feb 19, 2004 | Issued |
Array
(
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[patent_title] => 'Method for bridging a upnp network and a havi network'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708242 | Redundant external storage virtualization computer system | Feb 17, 2004 | Issued |
Array
(
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[patent_title] => 'Data transfer method for Universal Serial Bus device'
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[firstpage_image] =>[orig_patent_app_number] => 10708174
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708174 | Data transfer method for Universal Serial Bus device | Feb 12, 2004 | Issued |