Search

Sam Silverberg

Examiner (ID: 4104)

Most Active Art Unit
1502
Art Unit(s)
1308, 1309, 1101, 1742, 1502, 1311, 1733, 1102, 1305, 1304
Total Applications
1075
Issued Applications
889
Pending Applications
40
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6264067 [patent_doc_number] => 20100252855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'SEMICONDUCTOR LIGHT-EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/742559 [patent_app_country] => US [patent_app_date] => 2008-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5190 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20100252855.pdf [firstpage_image] =>[orig_patent_app_number] => 12742559 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/742559
SEMICONDUCTOR LIGHT-EMITTING DEVICE Nov 12, 2008 Abandoned
Array ( [id] => 8690575 [patent_doc_number] => 08390104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Semiconductor apparatus packaging structure having embossed tape over tab tape, the embossed tape and method of forming the semiconductor apparatus packaging structure' [patent_app_type] => utility [patent_app_number] => 12/734510 [patent_app_country] => US [patent_app_date] => 2008-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 13397 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12734510 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/734510
Semiconductor apparatus packaging structure having embossed tape over tab tape, the embossed tape and method of forming the semiconductor apparatus packaging structure Nov 6, 2008 Issued
Array ( [id] => 5262324 [patent_doc_number] => 20090115009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Multibit electro-mechanical memory device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/289851 [patent_app_country] => US [patent_app_date] => 2008-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115009.pdf [firstpage_image] =>[orig_patent_app_number] => 12289851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/289851
Multibit electro-mechanical memory device having at least one cantilever electrode and at least one gate line and manufacturing method thereof Nov 5, 2008 Issued
Array ( [id] => 5499334 [patent_doc_number] => 20090160022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'METHOD OF FABRICATING MIM STRUCTURE CAPACITOR' [patent_app_type] => utility [patent_app_number] => 12/264745 [patent_app_country] => US [patent_app_date] => 2008-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1942 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20090160022.pdf [firstpage_image] =>[orig_patent_app_number] => 12264745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/264745
METHOD OF FABRICATING MIM STRUCTURE CAPACITOR Nov 3, 2008 Abandoned
Array ( [id] => 5278688 [patent_doc_number] => 20090130820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/263525 [patent_app_country] => US [patent_app_date] => 2008-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20090130820.pdf [firstpage_image] =>[orig_patent_app_number] => 12263525 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/263525
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Nov 2, 2008 Abandoned
Array ( [id] => 6336865 [patent_doc_number] => 20100019379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'EXTERNAL HEAT SINK FOR BARE-DIE FLIP CHIP PACKAGES' [patent_app_type] => utility [patent_app_number] => 12/261407 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10502 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019379.pdf [firstpage_image] =>[orig_patent_app_number] => 12261407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/261407
EXTERNAL HEAT SINK FOR BARE-DIE FLIP CHIP PACKAGES Oct 29, 2008 Abandoned
Array ( [id] => 5262323 [patent_doc_number] => 20090115008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'MANUFACTURING METHOD OF AN ELECTRONIC DEVICE INCLUDING OVERMOLDED MEMS DEVICES' [patent_app_type] => utility [patent_app_number] => 12/260910 [patent_app_country] => US [patent_app_date] => 2008-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4362 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115008.pdf [firstpage_image] =>[orig_patent_app_number] => 12260910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/260910
MANUFACTURING METHOD OF AN ELECTRONIC DEVICE INCLUDING OVERMOLDED MEMS DEVICES Oct 28, 2008 Abandoned
Array ( [id] => 8759946 [patent_doc_number] => 08420466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Method of forming TFT floating gate memory cell structures' [patent_app_type] => utility [patent_app_number] => 12/259165 [patent_app_country] => US [patent_app_date] => 2008-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6717 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12259165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/259165
Method of forming TFT floating gate memory cell structures Oct 26, 2008 Issued
Array ( [id] => 8749387 [patent_doc_number] => 08415218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Atomic layer deposition epitaxial silicon growth for TFT flash memory cell' [patent_app_type] => utility [patent_app_number] => 12/259128 [patent_app_country] => US [patent_app_date] => 2008-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6364 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12259128 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/259128
Atomic layer deposition epitaxial silicon growth for TFT flash memory cell Oct 26, 2008 Issued
Array ( [id] => 6609384 [patent_doc_number] => 20100099247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'FLASH MEMORY WITH TREATED CHARGE TRAP LAYER' [patent_app_type] => utility [patent_app_number] => 12/256173 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8839 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20100099247.pdf [firstpage_image] =>[orig_patent_app_number] => 12256173 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/256173
Method of forming flash memory with ultraviolet treatment Oct 21, 2008 Issued
Array ( [id] => 6575194 [patent_doc_number] => 20100096688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'NON-VOLATILE MEMORY HAVING CHARGE TRAP LAYER WITH COMPOSITIONAL GRADIENT' [patent_app_type] => utility [patent_app_number] => 12/256119 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8837 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20100096688.pdf [firstpage_image] =>[orig_patent_app_number] => 12256119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/256119
Method of forming non-volatile memory having charge trap layer with compositional gradient Oct 21, 2008 Issued
Array ( [id] => 6575177 [patent_doc_number] => 20100096687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'NON-VOLATILE MEMORY HAVING SILICON NITRIDE CHARGE TRAP LAYER' [patent_app_type] => utility [patent_app_number] => 12/255617 [patent_app_country] => US [patent_app_date] => 2008-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8802 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20100096687.pdf [firstpage_image] =>[orig_patent_app_number] => 12255617 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/255617
Method of forming a non-volatile memory having a silicon nitride charge trap layer Oct 20, 2008 Issued
Array ( [id] => 5572935 [patent_doc_number] => 20090140296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Epitaxial Growth of Cubic Crystalline Semiconductor Alloys on Basal Plane of Trigonal or Hexagonal Crystal' [patent_app_type] => utility [patent_app_number] => 12/254017 [patent_app_country] => US [patent_app_date] => 2008-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7499 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140296.pdf [firstpage_image] =>[orig_patent_app_number] => 12254017 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/254017
Epitaxial growth of cubic crystalline semiconductor alloys on basal plane of trigonal or hexagonal crystal Oct 19, 2008 Issued
Array ( [id] => 5284995 [patent_doc_number] => 20090098670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'SEMICONDUCTOR DEVICE FOR MONITORING CURRENT CHARACTERISTIC AND MONITORING METHOD FOR CURRENT CHARACTERISTIC OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/249088 [patent_app_country] => US [patent_app_date] => 2008-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20090098670.pdf [firstpage_image] =>[orig_patent_app_number] => 12249088 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/249088
SEMICONDUCTOR DEVICE FOR MONITORING CURRENT CHARACTERISTIC AND MONITORING METHOD FOR CURRENT CHARACTERISTIC OF SEMICONDUCTOR DEVICE Oct 9, 2008 Abandoned
Array ( [id] => 4570302 [patent_doc_number] => 07847341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Electron blocking layers for electronic devices' [patent_app_type] => utility [patent_app_number] => 12/247917 [patent_app_country] => US [patent_app_date] => 2008-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 14919 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/847/07847341.pdf [firstpage_image] =>[orig_patent_app_number] => 12247917 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/247917
Electron blocking layers for electronic devices Oct 7, 2008 Issued
Array ( [id] => 9323305 [patent_doc_number] => 08658323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Solid oxide fuel cell generation system' [patent_app_type] => utility [patent_app_number] => 12/246600 [patent_app_country] => US [patent_app_date] => 2008-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7656 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12246600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/246600
Solid oxide fuel cell generation system Oct 6, 2008 Issued
Array ( [id] => 63583 [patent_doc_number] => 07763924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Dynamic random access memory structure having merged trench and stack capacitors' [patent_app_type] => utility [patent_app_number] => 12/244747 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3234 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763924.pdf [firstpage_image] =>[orig_patent_app_number] => 12244747 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/244747
Dynamic random access memory structure having merged trench and stack capacitors Oct 1, 2008 Issued
Array ( [id] => 8257558 [patent_doc_number] => 08207036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Method for forming self-aligned dielectric cap above floating gate' [patent_app_type] => utility [patent_app_number] => 12/242857 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 9504 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12242857 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242857
Method for forming self-aligned dielectric cap above floating gate Sep 29, 2008 Issued
Array ( [id] => 8202880 [patent_doc_number] => 08188550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Integrated circuit structure with electrical strap and its method of forming' [patent_app_type] => utility [patent_app_number] => 12/241105 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5222 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/188/08188550.pdf [firstpage_image] =>[orig_patent_app_number] => 12241105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/241105
Integrated circuit structure with electrical strap and its method of forming Sep 29, 2008 Issued
Array ( [id] => 6359002 [patent_doc_number] => 20100078814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'SYSTEM AND METHOD FOR USING POROUS LOW DIELECTRIC FILMS' [patent_app_type] => utility [patent_app_number] => 12/240627 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20100078814.pdf [firstpage_image] =>[orig_patent_app_number] => 12240627 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/240627
SYSTEM AND METHOD FOR USING POROUS LOW DIELECTRIC FILMS Sep 28, 2008 Abandoned
Menu