
Sam Silverberg
Examiner (ID: 4104)
| Most Active Art Unit | 1502 |
| Art Unit(s) | 1308, 1309, 1101, 1742, 1502, 1311, 1733, 1102, 1305, 1304 |
| Total Applications | 1075 |
| Issued Applications | 889 |
| Pending Applications | 40 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5493388
[patent_doc_number] => 20090261416
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-22
[patent_title] => 'INTEGRATED MEMS DEVICE AND CONTROL CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/105989
[patent_app_country] => US
[patent_app_date] => 2008-04-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/105989 | INTEGRATED MEMS DEVICE AND CONTROL CIRCUIT | Apr 17, 2008 | Abandoned |
Array
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[patent_doc_number] => 20090134442
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[patent_kind] => A1
[patent_issue_date] => 2009-05-28
[patent_title] => 'RECESSED CHANNEL DEVICE AND METHOD THEREOF'
[patent_app_type] => utility
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[patent_app_date] => 2008-04-15
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Array
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[patent_issue_date] => 2008-08-14
[patent_title] => 'METHOD FOR FABRICATING A NONVOLATILE MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/102710
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Array
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[patent_doc_number] => 20080191266
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[patent_issue_date] => 2008-08-14
[patent_title] => 'Highly reliable NAND flash memory using a five side enclosed floating gate storage elements'
[patent_app_type] => utility
[patent_app_number] => 12/082199
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[patent_app_date] => 2008-04-10
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Array
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[patent_title] => 'Fuse structure, and semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/081012 | Fuse structure, and semiconductor device | Apr 8, 2008 | Abandoned |
Array
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[patent_doc_number] => 20090253238
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[patent_issue_date] => 2009-10-08
[patent_title] => 'METHOD OF FORMING MULTIPLE FINS FOR A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/099726
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/099726 | Method of forming multiple fins for a semiconductor device | Apr 7, 2008 | Issued |
Array
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[patent_title] => 'Integrated circuit edge protection method and apparatus'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/062400 | Integrated circuit edge protection method and apparatus | Apr 2, 2008 | Issued |
Array
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[patent_doc_number] => 07825007
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[patent_issue_date] => 2010-11-02
[patent_title] => 'Method of joining a plurality of SOI substrates on a glass substrate by a heat treatment'
[patent_app_type] => utility
[patent_app_number] => 12/078410
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Array
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[id] => 4778913
[patent_doc_number] => 20080286911
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[patent_title] => 'Method for manufacturing semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/078215 | Method for manufacturing semiconductor device by applying laser beam to single-crystal semiconductor layer and non-single-crystal semiconductor layer through cap film | Mar 27, 2008 | Issued |
Array
(
[id] => 5401418
[patent_doc_number] => 20090236731
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[patent_issue_date] => 2009-09-24
[patent_title] => 'STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/051469
[patent_app_country] => US
[patent_app_date] => 2008-03-19
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[firstpage_image] =>[orig_patent_app_number] => 12051469
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/051469 | Stackable integrated circuit package system | Mar 18, 2008 | Issued |
Array
(
[id] => 5401345
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[patent_title] => 'ARRAY OF VERTICAL TRIGATE TRANSISTORS AND METHOD OF PRODUCTION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/050230 | ARRAY OF VERTICAL TRIGATE TRANSISTORS AND METHOD OF PRODUCTION | Mar 17, 2008 | Abandoned |
Array
(
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Array
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Array
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Array
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Array
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