
Samantha N. Wood
Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )
| Most Active Art Unit | 2915 |
| Art Unit(s) | 2914, 2915 |
| Total Applications | 1312 |
| Issued Applications | 1235 |
| Pending Applications | 29 |
| Abandoned Applications | 58 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8275084
[patent_doc_number] => 20120168943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-05
[patent_title] => 'PLASMA TREATMENT ON SEMICONDUCTOR WAFERS'
[patent_app_type] => utility
[patent_app_number] => 12/982719
[patent_app_country] => US
[patent_app_date] => 2010-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3746
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982719
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/982719 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS | Dec 29, 2010 | Abandoned |
Array
(
[id] => 8439581
[patent_doc_number] => 20120256197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-11
[patent_title] => 'ORGANIC ELECTROLUMINESCENCE ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 13/515313
[patent_app_country] => US
[patent_app_date] => 2010-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6443
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13515313
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/515313 | ORGANIC ELECTROLUMINESCENCE ELEMENT | Dec 15, 2010 | Abandoned |
Array
(
[id] => 8227962
[patent_doc_number] => 20120142146
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-07
[patent_title] => 'METHOD OF MANUFACTURING LAYERED CHIP PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/960921
[patent_app_country] => US
[patent_app_date] => 2010-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 24782
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12960921
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/960921 | Method of manufacturing layered chip package | Dec 5, 2010 | Issued |
Array
(
[id] => 8582773
[patent_doc_number] => 20130001594
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => 'Electronic Device'
[patent_app_type] => utility
[patent_app_number] => 13/512153
[patent_app_country] => US
[patent_app_date] => 2010-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2388
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13512153
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/512153 | Electronic device | Dec 5, 2010 | Issued |
Array
(
[id] => 10506413
[patent_doc_number] => 09234281
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-12
[patent_title] => 'Method for producing silicon layers'
[patent_app_type] => utility
[patent_app_number] => 13/510373
[patent_app_country] => US
[patent_app_date] => 2010-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4452
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13510373
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/510373 | Method for producing silicon layers | Nov 9, 2010 | Issued |
Array
(
[id] => 8470287
[patent_doc_number] => 08299466
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-30
[patent_title] => 'Thin film transistors having multiple doped silicon layers'
[patent_app_type] => utility
[patent_app_number] => 12/913846
[patent_app_country] => US
[patent_app_date] => 2010-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5124
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913846
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/913846 | Thin film transistors having multiple doped silicon layers | Oct 27, 2010 | Issued |
Array
(
[id] => 8591203
[patent_doc_number] => 08349078
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-08
[patent_title] => 'Method of forming nitride semiconductor epitaxial layer and method of manufacturing nitride semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/913062
[patent_app_country] => US
[patent_app_date] => 2010-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 28
[patent_no_of_words] => 18794
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913062
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/913062 | Method of forming nitride semiconductor epitaxial layer and method of manufacturing nitride semiconductor device | Oct 26, 2010 | Issued |
Array
(
[id] => 8164337
[patent_doc_number] => 08173527
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-08
[patent_title] => 'Stepped masking for patterned implantation'
[patent_app_type] => utility
[patent_app_number] => 12/906369
[patent_app_country] => US
[patent_app_date] => 2010-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 6044
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/173/08173527.pdf
[firstpage_image] =>[orig_patent_app_number] => 12906369
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/906369 | Stepped masking for patterned implantation | Oct 17, 2010 | Issued |
Array
(
[id] => 6047715
[patent_doc_number] => 20110207264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-25
[patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/905395
[patent_app_country] => US
[patent_app_date] => 2010-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 13119
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0207/20110207264.pdf
[firstpage_image] =>[orig_patent_app_number] => 12905395
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/905395 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | Oct 14, 2010 | Abandoned |
Array
(
[id] => 10888038
[patent_doc_number] => 08912033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-16
[patent_title] => 'Dicing-free LED fabrication'
[patent_app_type] => utility
[patent_app_number] => 12/900663
[patent_app_country] => US
[patent_app_date] => 2010-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4380
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12900663
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/900663 | Dicing-free LED fabrication | Oct 7, 2010 | Issued |
Array
(
[id] => 8199372
[patent_doc_number] => 08187343
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-29
[patent_title] => 'Methods of manufacturing electric double layer capacitor cell and electric double layer capacitor and apparatus for manufacturing electric double layer capacitor cell'
[patent_app_type] => utility
[patent_app_number] => 12/923829
[patent_app_country] => US
[patent_app_date] => 2010-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 5039
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/187/08187343.pdf
[firstpage_image] =>[orig_patent_app_number] => 12923829
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/923829 | Methods of manufacturing electric double layer capacitor cell and electric double layer capacitor and apparatus for manufacturing electric double layer capacitor cell | Oct 7, 2010 | Issued |
Array
(
[id] => 10010413
[patent_doc_number] => 09053938
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-06-09
[patent_title] => 'High light transmission, low sheet resistance layer for photovoltaic devices'
[patent_app_type] => utility
[patent_app_number] => 12/901470
[patent_app_country] => US
[patent_app_date] => 2010-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 6829
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12901470
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/901470 | High light transmission, low sheet resistance layer for photovoltaic devices | Oct 7, 2010 | Issued |
Array
(
[id] => 6143620
[patent_doc_number] => 20110129972
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-02
[patent_title] => 'TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED ON THE BASIS OF A SIMPLIFIED SPACER REGIME'
[patent_app_type] => utility
[patent_app_number] => 12/899333
[patent_app_country] => US
[patent_app_date] => 2010-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8272
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0129/20110129972.pdf
[firstpage_image] =>[orig_patent_app_number] => 12899333
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/899333 | Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime | Oct 5, 2010 | Issued |
Array
(
[id] => 6126792
[patent_doc_number] => 20110086468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-14
[patent_title] => 'ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS'
[patent_app_type] => utility
[patent_app_number] => 12/898028
[patent_app_country] => US
[patent_app_date] => 2010-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1526
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20110086468.pdf
[firstpage_image] =>[orig_patent_app_number] => 12898028
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/898028 | ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS | Oct 4, 2010 | Abandoned |
Array
(
[id] => 8363546
[patent_doc_number] => 08252611
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-28
[patent_title] => 'Buffer layer and manufacturing method thereof, reaction solution, photoelectric conversion device, and solar cell'
[patent_app_type] => utility
[patent_app_number] => 12/898403
[patent_app_country] => US
[patent_app_date] => 2010-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 13306
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12898403
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/898403 | Buffer layer and manufacturing method thereof, reaction solution, photoelectric conversion device, and solar cell | Oct 4, 2010 | Issued |
Array
(
[id] => 6067760
[patent_doc_number] => 20110042750
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-24
[patent_title] => 'CONTROLLING GATE FORMATION FOR HIGH DENSITY CELL LAYOUT'
[patent_app_type] => utility
[patent_app_number] => 12/897559
[patent_app_country] => US
[patent_app_date] => 2010-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8152
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20110042750.pdf
[firstpage_image] =>[orig_patent_app_number] => 12897559
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/897559 | Controlling gate formation for high density cell layout | Oct 3, 2010 | Issued |
Array
(
[id] => 6032315
[patent_doc_number] => 20110081771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-07
[patent_title] => 'MULTICHAMBER SPLIT PROCESSES FOR LED MANUFACTURING'
[patent_app_type] => utility
[patent_app_number] => 12/897429
[patent_app_country] => US
[patent_app_date] => 2010-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10488
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20110081771.pdf
[firstpage_image] =>[orig_patent_app_number] => 12897429
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/897429 | MULTICHAMBER SPLIT PROCESSES FOR LED MANUFACTURING | Oct 3, 2010 | Abandoned |
Array
(
[id] => 8095039
[patent_doc_number] => 20120083127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'METHOD FOR FORMING A PATTERN AND A SEMICONDUCTOR DEVICE MANUFACTURING METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/895507
[patent_app_country] => US
[patent_app_date] => 2010-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7092
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20120083127.pdf
[firstpage_image] =>[orig_patent_app_number] => 12895507
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/895507 | METHOD FOR FORMING A PATTERN AND A SEMICONDUCTOR DEVICE MANUFACTURING METHOD | Sep 29, 2010 | Abandoned |
Array
(
[id] => 6015913
[patent_doc_number] => 20110223744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-15
[patent_title] => 'METHOD FOR MANUFACTURING AN OPTICAL SEMICONDUCTOR DEVICE AND COMPOSITION FOR FORMING A PROTECTIVE LAYER OF AN OPTICAL SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/892193
[patent_app_country] => US
[patent_app_date] => 2010-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 9871
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0223/20110223744.pdf
[firstpage_image] =>[orig_patent_app_number] => 12892193
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/892193 | METHOD FOR MANUFACTURING AN OPTICAL SEMICONDUCTOR DEVICE AND COMPOSITION FOR FORMING A PROTECTIVE LAYER OF AN OPTICAL SEMICONDUCTOR DEVICE | Sep 27, 2010 | Abandoned |
Array
(
[id] => 8386095
[patent_doc_number] => 08263490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-09-11
[patent_title] => 'Formation method of metallic electrode of semiconductor device and metallic electrode formation apparatus'
[patent_app_type] => utility
[patent_app_number] => 12/923576
[patent_app_country] => US
[patent_app_date] => 2010-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 28
[patent_no_of_words] => 15623
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 455
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12923576
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/923576 | Formation method of metallic electrode of semiconductor device and metallic electrode formation apparatus | Sep 27, 2010 | Issued |