Search

Samantha N. Wood

Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )

Most Active Art Unit
2915
Art Unit(s)
2914, 2915
Total Applications
1312
Issued Applications
1235
Pending Applications
29
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8146654 [patent_doc_number] => 08163659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Method for oxide film formation and apparatus for the method' [patent_app_type] => utility [patent_app_number] => 12/438605 [patent_app_country] => US [patent_app_date] => 2007-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8965 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/163/08163659.pdf [firstpage_image] =>[orig_patent_app_number] => 12438605 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/438605
Method for oxide film formation and apparatus for the method Aug 21, 2007 Issued
Array ( [id] => 6490217 [patent_doc_number] => 20100009548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'METHOD FOR HEAT-TREATING SILICON WAFER' [patent_app_type] => utility [patent_app_number] => 12/438786 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7832 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20100009548.pdf [firstpage_image] =>[orig_patent_app_number] => 12438786 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/438786
METHOD FOR HEAT-TREATING SILICON WAFER Aug 20, 2007 Abandoned
Array ( [id] => 7551067 [patent_doc_number] => 08063401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Testing for correct undercutting of an electrode during an etching step' [patent_app_type] => utility [patent_app_number] => 12/377735 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6774 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/063/08063401.pdf [firstpage_image] =>[orig_patent_app_number] => 12377735 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/377735
Testing for correct undercutting of an electrode during an etching step Aug 13, 2007 Issued
Array ( [id] => 4651590 [patent_doc_number] => 20080038846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Method of fabricating a capacitor of a memory device' [patent_app_type] => utility [patent_app_number] => 11/878868 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4538 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20080038846.pdf [firstpage_image] =>[orig_patent_app_number] => 11878868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/878868
Method of fabricating a capacitor of a memory device Jul 26, 2007 Abandoned
Array ( [id] => 4648651 [patent_doc_number] => 20080035906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'GERMANIUM COMPOUND, SEMICONDUCTOR DEVICE FABRICATED USING THE SAME, AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/777854 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5647 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20080035906.pdf [firstpage_image] =>[orig_patent_app_number] => 11777854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/777854
Germanium compound, semiconductor device fabricated using the same, and methods of forming the same Jul 12, 2007 Issued
Array ( [id] => 5225172 [patent_doc_number] => 20070254438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 11/774663 [patent_app_country] => US [patent_app_date] => 2007-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20070254438.pdf [firstpage_image] =>[orig_patent_app_number] => 11774663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774663
Double gated transistor and method of fabrication Jul 8, 2007 Issued
Array ( [id] => 5358130 [patent_doc_number] => 20090032924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'HERMETICALLY SEALED PACKAGE WITH WINDOW' [patent_app_type] => utility [patent_app_number] => 11/773354 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17545 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20090032924.pdf [firstpage_image] =>[orig_patent_app_number] => 11773354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/773354
HERMETICALLY SEALED PACKAGE WITH WINDOW Jul 2, 2007 Abandoned
Array ( [id] => 8555063 [patent_doc_number] => 08329535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Multi-level-cell trapping DRAM' [patent_app_type] => utility [patent_app_number] => 11/761344 [patent_app_country] => US [patent_app_date] => 2007-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3031 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11761344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/761344
Multi-level-cell trapping DRAM Jun 10, 2007 Issued
Array ( [id] => 5129115 [patent_doc_number] => 20070205512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Solder bump structure for flip chip package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/785980 [patent_app_country] => US [patent_app_date] => 2007-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3541 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20070205512.pdf [firstpage_image] =>[orig_patent_app_number] => 11785980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785980
Solder bump structure for flip chip package and method for manufacturing the same Apr 22, 2007 Abandoned
Array ( [id] => 4662258 [patent_doc_number] => 20080253165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Method of Manufacturing a Memory Device, Memory Device, Cell, Integrated Circuit, Memory Module, and Computing System' [patent_app_type] => utility [patent_app_number] => 11/733696 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8666 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20080253165.pdf [firstpage_image] =>[orig_patent_app_number] => 11733696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733696
Method of Manufacturing a Memory Device, Memory Device, Cell, Integrated Circuit, Memory Module, and Computing System Apr 9, 2007 Abandoned
Array ( [id] => 4682372 [patent_doc_number] => 20080248598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'METHOD AND APPARATUS FOR DETERMINING CHARACTERISTICS OF A STRESSED MATERIAL USING SCATTEROMETRY' [patent_app_type] => utility [patent_app_number] => 11/697955 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5733 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20080248598.pdf [firstpage_image] =>[orig_patent_app_number] => 11697955 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/697955
METHOD AND APPARATUS FOR DETERMINING CHARACTERISTICS OF A STRESSED MATERIAL USING SCATTEROMETRY Apr 8, 2007 Abandoned
Array ( [id] => 32514 [patent_doc_number] => 07790565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Semiconductor on glass insulator made using improved thinning process' [patent_app_type] => utility [patent_app_number] => 11/729895 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6045 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790565.pdf [firstpage_image] =>[orig_patent_app_number] => 11729895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/729895
Semiconductor on glass insulator made using improved thinning process Mar 28, 2007 Issued
Array ( [id] => 7692003 [patent_doc_number] => 20070232030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Semiconductor-wafer processing method using fluid-like layer' [patent_app_type] => utility [patent_app_number] => 11/727303 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232030.pdf [firstpage_image] =>[orig_patent_app_number] => 11727303 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727303
Semiconductor-wafer processing method using fluid-like layer Mar 25, 2007 Abandoned
Array ( [id] => 5116934 [patent_doc_number] => 20070138648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Schottky Diode Device with Aluminum Pickup of Backside Cathode' [patent_app_type] => utility [patent_app_number] => 11/676066 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4756 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138648.pdf [firstpage_image] =>[orig_patent_app_number] => 11676066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/676066
Schottky Diode Device with Aluminum Pickup of Backside Cathode Feb 15, 2007 Abandoned
Array ( [id] => 8104919 [patent_doc_number] => 08154107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Semiconductor device and a method of fabricating the device' [patent_app_type] => utility [patent_app_number] => 11/703365 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 4996 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/154/08154107.pdf [firstpage_image] =>[orig_patent_app_number] => 11703365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703365
Semiconductor device and a method of fabricating the device Feb 6, 2007 Issued
Array ( [id] => 42611 [patent_doc_number] => 07781302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions' [patent_app_type] => utility [patent_app_number] => 11/703316 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4459 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781302.pdf [firstpage_image] =>[orig_patent_app_number] => 11703316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703316
Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions Feb 6, 2007 Issued
Array ( [id] => 33211 [patent_doc_number] => 07785971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-31 [patent_title] => 'Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage' [patent_app_type] => utility [patent_app_number] => 11/703350 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 69 [patent_no_of_words] => 48437 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/785/07785971.pdf [firstpage_image] =>[orig_patent_app_number] => 11703350 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703350
Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage Feb 5, 2007 Issued
Array ( [id] => 5236728 [patent_doc_number] => 20070128885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/699984 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8002 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128885.pdf [firstpage_image] =>[orig_patent_app_number] => 11699984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699984
Method for fabricating a semiconductor device Jan 30, 2007 Abandoned
Array ( [id] => 5177576 [patent_doc_number] => 20070178636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/699584 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3016 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20070178636.pdf [firstpage_image] =>[orig_patent_app_number] => 11699584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699584
Method of manufacturing semiconductor device Jan 29, 2007 Issued
Array ( [id] => 4843307 [patent_doc_number] => 20080179715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Shallow trench isolation using atomic layer deposition during fabrication of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/699876 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6376 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179715.pdf [firstpage_image] =>[orig_patent_app_number] => 11699876 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699876
Shallow trench isolation using atomic layer deposition during fabrication of a semiconductor device Jan 29, 2007 Abandoned
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