
Samantha N. Wood
Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )
| Most Active Art Unit | 2915 |
| Art Unit(s) | 2914, 2915 |
| Total Applications | 1312 |
| Issued Applications | 1235 |
| Pending Applications | 29 |
| Abandoned Applications | 58 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8146654
[patent_doc_number] => 08163659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-24
[patent_title] => 'Method for oxide film formation and apparatus for the method'
[patent_app_type] => utility
[patent_app_number] => 12/438605
[patent_app_country] => US
[patent_app_date] => 2007-08-22
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[pdf_file] => patents/08/163/08163659.pdf
[firstpage_image] =>[orig_patent_app_number] => 12438605
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/438605 | Method for oxide film formation and apparatus for the method | Aug 21, 2007 | Issued |
Array
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[patent_doc_number] => 20100009548
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[patent_issue_date] => 2010-01-14
[patent_title] => 'METHOD FOR HEAT-TREATING SILICON WAFER'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/438786 | METHOD FOR HEAT-TREATING SILICON WAFER | Aug 20, 2007 | Abandoned |
Array
(
[id] => 7551067
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[patent_issue_date] => 2011-11-22
[patent_title] => 'Testing for correct undercutting of an electrode during an etching step'
[patent_app_type] => utility
[patent_app_number] => 12/377735
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[pdf_file] => patents/08/063/08063401.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/377735 | Testing for correct undercutting of an electrode during an etching step | Aug 13, 2007 | Issued |
Array
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[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'Method of fabricating a capacitor of a memory device'
[patent_app_type] => utility
[patent_app_number] => 11/878868
[patent_app_country] => US
[patent_app_date] => 2007-07-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/878868 | Method of fabricating a capacitor of a memory device | Jul 26, 2007 | Abandoned |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'GERMANIUM COMPOUND, SEMICONDUCTOR DEVICE FABRICATED USING THE SAME, AND METHODS OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/777854
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/777854 | Germanium compound, semiconductor device fabricated using the same, and methods of forming the same | Jul 12, 2007 | Issued |
Array
(
[id] => 5225172
[patent_doc_number] => 20070254438
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[patent_issue_date] => 2007-11-01
[patent_title] => 'DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION'
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[patent_app_number] => 11/774663
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[firstpage_image] =>[orig_patent_app_number] => 11774663
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/774663 | Double gated transistor and method of fabrication | Jul 8, 2007 | Issued |
Array
(
[id] => 5358130
[patent_doc_number] => 20090032924
[patent_country] => US
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[patent_issue_date] => 2009-02-05
[patent_title] => 'HERMETICALLY SEALED PACKAGE WITH WINDOW'
[patent_app_type] => utility
[patent_app_number] => 11/773354
[patent_app_country] => US
[patent_app_date] => 2007-07-03
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[patent_drawing_sheets_cnt] => 14
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[pdf_file] => publications/A1/0032/20090032924.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/773354 | HERMETICALLY SEALED PACKAGE WITH WINDOW | Jul 2, 2007 | Abandoned |
Array
(
[id] => 8555063
[patent_doc_number] => 08329535
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-11
[patent_title] => 'Multi-level-cell trapping DRAM'
[patent_app_type] => utility
[patent_app_number] => 11/761344
[patent_app_country] => US
[patent_app_date] => 2007-06-11
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11761344
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/761344 | Multi-level-cell trapping DRAM | Jun 10, 2007 | Issued |
Array
(
[id] => 5129115
[patent_doc_number] => 20070205512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-06
[patent_title] => 'Solder bump structure for flip chip package and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/785980
[patent_app_country] => US
[patent_app_date] => 2007-04-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/785980 | Solder bump structure for flip chip package and method for manufacturing the same | Apr 22, 2007 | Abandoned |
Array
(
[id] => 4662258
[patent_doc_number] => 20080253165
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[patent_issue_date] => 2008-10-16
[patent_title] => 'Method of Manufacturing a Memory Device, Memory Device, Cell, Integrated Circuit, Memory Module, and Computing System'
[patent_app_type] => utility
[patent_app_number] => 11/733696
[patent_app_country] => US
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Array
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[patent_doc_number] => 20080248598
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[patent_title] => 'METHOD AND APPARATUS FOR DETERMINING CHARACTERISTICS OF A STRESSED MATERIAL USING SCATTEROMETRY'
[patent_app_type] => utility
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Array
(
[id] => 32514
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[patent_issue_date] => 2010-09-07
[patent_title] => 'Semiconductor on glass insulator made using improved thinning process'
[patent_app_type] => utility
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Array
(
[id] => 7692003
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[patent_issue_date] => 2007-10-04
[patent_title] => 'Semiconductor-wafer processing method using fluid-like layer'
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Array
(
[id] => 5116934
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[patent_title] => 'Schottky Diode Device with Aluminum Pickup of Backside Cathode'
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Array
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Array
(
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[patent_issue_date] => 2010-08-24
[patent_title] => 'Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions'
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Array
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Array
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