Search

Samantha N. Wood

Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )

Most Active Art Unit
2915
Art Unit(s)
2914, 2915
Total Applications
1312
Issued Applications
1235
Pending Applications
29
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4843254 [patent_doc_number] => 20080179662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Closed trench MOSFET with floating trench rings as termination' [patent_app_type] => utility [patent_app_number] => 11/699256 [patent_app_country] => US [patent_app_date] => 2007-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179662.pdf [firstpage_image] =>[orig_patent_app_number] => 11699256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699256
Closed trench MOSFET with floating trench rings as termination Jan 27, 2007 Issued
Array ( [id] => 5110440 [patent_doc_number] => 20070194355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Transistor device with two planar gates and fabrication process' [patent_app_type] => utility [patent_app_number] => 11/698755 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3515 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194355.pdf [firstpage_image] =>[orig_patent_app_number] => 11698755 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698755
Transistor device with two planar gates and fabrication process Jan 25, 2007 Issued
Array ( [id] => 7691956 [patent_doc_number] => 20070232077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/655883 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12435 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20070232077.pdf [firstpage_image] =>[orig_patent_app_number] => 11655883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655883
Method for manufacturing semiconductor device Jan 21, 2007 Issued
Array ( [id] => 5120021 [patent_doc_number] => 20070141735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'METHOD OF MONITORING DEPOSITION TEMPERATURE OF A COPPER SEED LAYER AND METHOD OF FORMING A COPPER LAYER' [patent_app_type] => utility [patent_app_number] => 11/610783 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1533 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20070141735.pdf [firstpage_image] =>[orig_patent_app_number] => 11610783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/610783
METHOD OF MONITORING DEPOSITION TEMPERATURE OF A COPPER SEED LAYER AND METHOD OF FORMING A COPPER LAYER Dec 13, 2006 Abandoned
Array ( [id] => 4829109 [patent_doc_number] => 20080128690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Scribe based bond pads for integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/607564 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128690.pdf [firstpage_image] =>[orig_patent_app_number] => 11607564 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607564
Scribe based bond pads for integrated circuits Nov 30, 2006 Issued
Array ( [id] => 914358 [patent_doc_number] => 07326648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-05 [patent_title] => 'Semiconductor device and fabrication process of forming silicide layer on a polysilicon pattern by reducing thickness of metal layer before forming silicide layer on the polysilicon pattern' [patent_app_type] => utility [patent_app_number] => 11/602241 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5357 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/326/07326648.pdf [firstpage_image] =>[orig_patent_app_number] => 11602241 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/602241
Semiconductor device and fabrication process of forming silicide layer on a polysilicon pattern by reducing thickness of metal layer before forming silicide layer on the polysilicon pattern Nov 20, 2006 Issued
Array ( [id] => 5505797 [patent_doc_number] => 20090079004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'METHOD FOR MAKING A TRANSISTOR WITH SELF-ALIGNED DOUBLE GATES BY REDUCING GATE PATTERNS' [patent_app_type] => utility [patent_app_number] => 11/561174 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10276 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20090079004.pdf [firstpage_image] =>[orig_patent_app_number] => 11561174 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561174
METHOD FOR MAKING A TRANSISTOR WITH SELF-ALIGNED DOUBLE GATES BY REDUCING GATE PATTERNS Nov 16, 2006 Abandoned
Array ( [id] => 4431916 [patent_doc_number] => 07968432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Laser processing apparatus and laser processing method' [patent_app_type] => utility [patent_app_number] => 11/598653 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 21000 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/968/07968432.pdf [firstpage_image] =>[orig_patent_app_number] => 11598653 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/598653
Laser processing apparatus and laser processing method Nov 13, 2006 Issued
Array ( [id] => 281756 [patent_doc_number] => 07553756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Process for producing semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/598084 [patent_app_country] => US [patent_app_date] => 2006-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 7305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/553/07553756.pdf [firstpage_image] =>[orig_patent_app_number] => 11598084 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/598084
Process for producing semiconductor integrated circuit device Nov 12, 2006 Issued
Array ( [id] => 7689338 [patent_doc_number] => 20070105360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Method of Forming Bump, Method of Forming Image Sensor Using the Method, Semiconductor Chip and the Sensor so Formed' [patent_app_type] => utility [patent_app_number] => 11/557753 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2434 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20070105360.pdf [firstpage_image] =>[orig_patent_app_number] => 11557753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557753
Method of Forming Bump, Method of Forming Image Sensor Using the Method, Semiconductor Chip and the Sensor so Formed Nov 7, 2006 Abandoned
Array ( [id] => 4971385 [patent_doc_number] => 20070111387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Manufacturing method of wiring board and manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/594074 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5847 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111387.pdf [firstpage_image] =>[orig_patent_app_number] => 11594074 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594074
Manufacturing method of wiring board and manufacturing method of semiconductor device Nov 7, 2006 Abandoned
Array ( [id] => 71557 [patent_doc_number] => 07754571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Method for forming a strained channel in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/592204 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/754/07754571.pdf [firstpage_image] =>[orig_patent_app_number] => 11592204 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/592204
Method for forming a strained channel in a semiconductor device Nov 2, 2006 Issued
Array ( [id] => 7689363 [patent_doc_number] => 20070105335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Monolithically integrated silicon and III-V electronics' [patent_app_type] => utility [patent_app_number] => 11/591383 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15011 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20070105335.pdf [firstpage_image] =>[orig_patent_app_number] => 11591383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/591383
Monolithically integrated silicon and III-V electronics Oct 31, 2006 Issued
Array ( [id] => 8527771 [patent_doc_number] => 08304342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Sacrificial CMP etch stop layer' [patent_app_type] => utility [patent_app_number] => 11/590133 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4504 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11590133 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590133
Sacrificial CMP etch stop layer Oct 30, 2006 Issued
Array ( [id] => 4893539 [patent_doc_number] => 20080102637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Method and semiconductor structure for reliability characterization' [patent_app_type] => utility [patent_app_number] => 11/590183 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20080102637.pdf [firstpage_image] =>[orig_patent_app_number] => 11590183 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590183
Method and semiconductor structure for reliability characterization Oct 30, 2006 Abandoned
Array ( [id] => 173814 [patent_doc_number] => 07659193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Conductive structures for electrically conductive pads of circuit board and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/588913 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3574 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/659/07659193.pdf [firstpage_image] =>[orig_patent_app_number] => 11588913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588913
Conductive structures for electrically conductive pads of circuit board and fabrication method thereof Oct 26, 2006 Issued
Array ( [id] => 5183130 [patent_doc_number] => 20070054484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR PACKAGES' [patent_app_type] => utility [patent_app_number] => 11/553098 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5556 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20070054484.pdf [firstpage_image] =>[orig_patent_app_number] => 11553098 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/553098
METHOD FOR FABRICATING SEMICONDUCTOR PACKAGES Oct 25, 2006 Abandoned
Array ( [id] => 7515291 [patent_doc_number] => 08039363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Small chips with fan-out leads' [patent_app_type] => utility [patent_app_number] => 11/588438 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3634 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/039/08039363.pdf [firstpage_image] =>[orig_patent_app_number] => 11588438 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588438
Small chips with fan-out leads Oct 25, 2006 Issued
Array ( [id] => 4965403 [patent_doc_number] => 20080108223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Integrated Etch and Supercritical CO2 Process and Chamber Design' [patent_app_type] => utility [patent_app_number] => 11/552364 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3232 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20080108223.pdf [firstpage_image] =>[orig_patent_app_number] => 11552364 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/552364
Integrated etch and supercritical CO2 process and chamber design Oct 23, 2006 Issued
Array ( [id] => 5040712 [patent_doc_number] => 20070092994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Method of manufacturing semiconductor device and a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/584624 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4336 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20070092994.pdf [firstpage_image] =>[orig_patent_app_number] => 11584624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584624
Method of manufacturing semiconductor device and a semiconductor device Oct 22, 2006 Abandoned
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