
Samantha N. Wood
Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )
| Most Active Art Unit | 2915 |
| Art Unit(s) | 2914, 2915 |
| Total Applications | 1312 |
| Issued Applications | 1235 |
| Pending Applications | 29 |
| Abandoned Applications | 58 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4523172
[patent_doc_number] => 07951670
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'Flash memory cell with split gate structure and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/368714
[patent_app_country] => US
[patent_app_date] => 2006-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 2910
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/951/07951670.pdf
[firstpage_image] =>[orig_patent_app_number] => 11368714
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/368714 | Flash memory cell with split gate structure and method for forming the same | Mar 5, 2006 | Issued |
Array
(
[id] => 5681939
[patent_doc_number] => 20060198209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'Nano memory, light, energy, antenna and strand-based systems and methods'
[patent_app_type] => utility
[patent_app_number] => 11/369103
[patent_app_country] => US
[patent_app_date] => 2006-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8549
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0198/20060198209.pdf
[firstpage_image] =>[orig_patent_app_number] => 11369103
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/369103 | Nano memory, light, energy, antenna and strand-based systems and methods | Mar 5, 2006 | Issued |
Array
(
[id] => 5628867
[patent_doc_number] => 20060145335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Method for manufacturing semiconductor device having a pair of heat sinks'
[patent_app_type] => utility
[patent_app_number] => 11/365674
[patent_app_country] => US
[patent_app_date] => 2006-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7193
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20060145335.pdf
[firstpage_image] =>[orig_patent_app_number] => 11365674
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/365674 | Method for manufacturing semiconductor device having a pair of heat sinks | Mar 1, 2006 | Abandoned |
Array
(
[id] => 5631645
[patent_doc_number] => 20060148115
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Method of fabricating vertical structure compound semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/367229
[patent_app_country] => US
[patent_app_date] => 2006-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4604
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20060148115.pdf
[firstpage_image] =>[orig_patent_app_number] => 11367229
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/367229 | Method of fabricating vertical structure compound semiconductor devices | Mar 1, 2006 | Issued |
Array
(
[id] => 5631645
[patent_doc_number] => 20060148115
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Method of fabricating vertical structure compound semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/367229
[patent_app_country] => US
[patent_app_date] => 2006-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4604
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20060148115.pdf
[firstpage_image] =>[orig_patent_app_number] => 11367229
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/367229 | Method of fabricating vertical structure compound semiconductor devices | Mar 1, 2006 | Issued |
Array
(
[id] => 5113056
[patent_doc_number] => 20070196971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-23
[patent_title] => 'Scalable embedded EEPROM memory cell'
[patent_app_type] => utility
[patent_app_number] => 11/359284
[patent_app_country] => US
[patent_app_date] => 2006-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3369
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0196/20070196971.pdf
[firstpage_image] =>[orig_patent_app_number] => 11359284
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/359284 | Scalable embedded EEPROM memory cell | Feb 21, 2006 | Abandoned |
Array
(
[id] => 5655910
[patent_doc_number] => 20060141646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Organic electroluminescent device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/357123
[patent_app_country] => US
[patent_app_date] => 2006-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6225
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20060141646.pdf
[firstpage_image] =>[orig_patent_app_number] => 11357123
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/357123 | Organic electroluminescent device and method of manufacturing the same | Feb 20, 2006 | Issued |
Array
(
[id] => 141914
[patent_doc_number] => 07691698
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-06
[patent_title] => 'Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain'
[patent_app_type] => utility
[patent_app_number] => 11/358483
[patent_app_country] => US
[patent_app_date] => 2006-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3058
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/691/07691698.pdf
[firstpage_image] =>[orig_patent_app_number] => 11358483
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/358483 | Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain | Feb 20, 2006 | Issued |
Array
(
[id] => 5685968
[patent_doc_number] => 20060284283
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-21
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/354854
[patent_app_country] => US
[patent_app_date] => 2006-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9321
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0284/20060284283.pdf
[firstpage_image] =>[orig_patent_app_number] => 11354854
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/354854 | Semiconductor device and manufacturing method thereof | Feb 15, 2006 | Abandoned |
Array
(
[id] => 557858
[patent_doc_number] => 07470614
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-12-30
[patent_title] => 'Methods for fabricating semiconductor devices and contacts to semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/355474
[patent_app_country] => US
[patent_app_date] => 2006-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 38
[patent_no_of_words] => 5757
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/470/07470614.pdf
[firstpage_image] =>[orig_patent_app_number] => 11355474
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/355474 | Methods for fabricating semiconductor devices and contacts to semiconductor devices | Feb 14, 2006 | Issued |
Array
(
[id] => 4752712
[patent_doc_number] => 20080160787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Method For Manufacturing a Thin-Layer Structure'
[patent_app_type] => utility
[patent_app_number] => 11/817474
[patent_app_country] => US
[patent_app_date] => 2006-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5523
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0160/20080160787.pdf
[firstpage_image] =>[orig_patent_app_number] => 11817474
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/817474 | Method For Manufacturing a Thin-Layer Structure | Feb 12, 2006 | Abandoned |
Array
(
[id] => 8282794
[patent_doc_number] => 08216896
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-10
[patent_title] => 'Method of forming STI regions in electronic devices'
[patent_app_type] => utility
[patent_app_number] => 11/816163
[patent_app_country] => US
[patent_app_date] => 2006-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3814
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11816163
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/816163 | Method of forming STI regions in electronic devices | Jan 31, 2006 | Issued |
Array
(
[id] => 5148835
[patent_doc_number] => 20070048895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'Method of manufacturing an organic electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/341799
[patent_app_country] => US
[patent_app_date] => 2006-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4221
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20070048895.pdf
[firstpage_image] =>[orig_patent_app_number] => 11341799
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/341799 | Method of manufacturing an organic electronic device | Jan 26, 2006 | Abandoned |
Array
(
[id] => 8103733
[patent_doc_number] => 08153515
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-10
[patent_title] => 'Methods of fabricating strain balanced nitride heterojunction transistors'
[patent_app_type] => utility
[patent_app_number] => 11/325735
[patent_app_country] => US
[patent_app_date] => 2006-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 6527
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/153/08153515.pdf
[firstpage_image] =>[orig_patent_app_number] => 11325735
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/325735 | Methods of fabricating strain balanced nitride heterojunction transistors | Jan 4, 2006 | Issued |
Array
(
[id] => 5628771
[patent_doc_number] => 20060145239
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Flash EEPROM device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/319484
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2141
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20060145239.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319484
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319484 | Flash EEPROM device and method for fabricating the same | Dec 28, 2005 | Issued |
Array
(
[id] => 5631725
[patent_doc_number] => 20060148195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Manufacturing isolation layer in CMOS image sensor'
[patent_app_type] => utility
[patent_app_number] => 11/319483
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1497
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20060148195.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319483
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319483 | Manufacturing isolation layer in CMOS image sensor | Dec 28, 2005 | Abandoned |
Array
(
[id] => 5631678
[patent_doc_number] => 20060148148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Semiconductor device manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 11/319264
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2540
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20060148148.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319264
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319264 | Semiconductor device manufacturing method | Dec 28, 2005 | Abandoned |
Array
(
[id] => 5596334
[patent_doc_number] => 20060160251
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Method in the fabrication of a memory device'
[patent_app_type] => utility
[patent_app_number] => 11/319383
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4188
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0160/20060160251.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319383
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319383 | Method in the fabrication of a memory device | Dec 28, 2005 | Abandoned |
Array
(
[id] => 5652756
[patent_doc_number] => 20060138491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Method for fabricating CMOS image sensor'
[patent_app_type] => utility
[patent_app_number] => 11/318504
[patent_app_country] => US
[patent_app_date] => 2005-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3298
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20060138491.pdf
[firstpage_image] =>[orig_patent_app_number] => 11318504
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/318504 | Method for fabricating CMOS image sensor | Dec 27, 2005 | Issued |
Array
(
[id] => 872005
[patent_doc_number] => 07361536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-22
[patent_title] => 'Method of fabrication of a field effect transistor with materialistically different two etch stop layers in an enhanced mode transistor and an depletion mode transistor'
[patent_app_type] => utility
[patent_app_number] => 11/319843
[patent_app_country] => US
[patent_app_date] => 2005-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4203
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/361/07361536.pdf
[firstpage_image] =>[orig_patent_app_number] => 11319843
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/319843 | Method of fabrication of a field effect transistor with materialistically different two etch stop layers in an enhanced mode transistor and an depletion mode transistor | Dec 27, 2005 | Issued |