Search

Samantha N. Wood

Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )

Most Active Art Unit
2915
Art Unit(s)
2914, 2915
Total Applications
1312
Issued Applications
1235
Pending Applications
29
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 823510 [patent_doc_number] => 07405103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Process for fabricating chip embedded package structure' [patent_app_type] => utility [patent_app_number] => 11/319844 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2986 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405103.pdf [firstpage_image] =>[orig_patent_app_number] => 11319844 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/319844
Process for fabricating chip embedded package structure Dec 26, 2005 Issued
Array ( [id] => 4994711 [patent_doc_number] => 20070010056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'NOR-type flash memory device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/315294 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2238 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20070010056.pdf [firstpage_image] =>[orig_patent_app_number] => 11315294 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/315294
NOR-type flash memory device and manufacturing method thereof Dec 22, 2005 Issued
Array ( [id] => 4546575 [patent_doc_number] => 07960226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness' [patent_app_type] => utility [patent_app_number] => 11/317694 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 6434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/960/07960226.pdf [firstpage_image] =>[orig_patent_app_number] => 11317694 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317694
Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness Dec 22, 2005 Issued
Array ( [id] => 5022927 [patent_doc_number] => 20070148893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method of forming a doped semiconductor portion' [patent_app_type] => utility [patent_app_number] => 11/314723 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4929 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148893.pdf [firstpage_image] =>[orig_patent_app_number] => 11314723 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314723
Method of forming a doped semiconductor portion Dec 21, 2005 Abandoned
Array ( [id] => 5022870 [patent_doc_number] => 20070148836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Reduced-resistance finFETs and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/316244 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148836.pdf [firstpage_image] =>[orig_patent_app_number] => 11316244 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/316244
Reduced-resistance finFETs by sidewall silicidation and methods of manufacturing the same Dec 21, 2005 Issued
Array ( [id] => 5022850 [patent_doc_number] => 20070148816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Attachment of a QFN to a PCB' [patent_app_type] => utility [patent_app_number] => 11/315613 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6946 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148816.pdf [firstpage_image] =>[orig_patent_app_number] => 11315613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/315613
Attachment of a QFN to a PCB Dec 21, 2005 Issued
Array ( [id] => 177828 [patent_doc_number] => 07655536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Methods of forming flash devices with shared word lines' [patent_app_type] => utility [patent_app_number] => 11/316474 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 35 [patent_no_of_words] => 10415 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/655/07655536.pdf [firstpage_image] =>[orig_patent_app_number] => 11316474 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/316474
Methods of forming flash devices with shared word lines Dec 20, 2005 Issued
Array ( [id] => 5656004 [patent_doc_number] => 20060141740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Semiconductor device with shallow trench isolation and a manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/316543 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141740.pdf [firstpage_image] =>[orig_patent_app_number] => 11316543 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/316543
Semiconductor device with shallow trench isolation and a manufacturing method thereof Dec 19, 2005 Abandoned
Array ( [id] => 585450 [patent_doc_number] => 07442653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Inter-metal dielectric of semiconductor device and manufacturing method thereof including plasma treating a plasma enhanced fluorosilicate glass' [patent_app_type] => utility [patent_app_number] => 11/316634 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1562 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442653.pdf [firstpage_image] =>[orig_patent_app_number] => 11316634 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/316634
Inter-metal dielectric of semiconductor device and manufacturing method thereof including plasma treating a plasma enhanced fluorosilicate glass Dec 19, 2005 Issued
Array ( [id] => 4971376 [patent_doc_number] => 20070111378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Method of protecting semiconductor chips from mechanical and ESD damage during handling' [patent_app_type] => utility [patent_app_number] => 11/280378 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1876 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111378.pdf [firstpage_image] =>[orig_patent_app_number] => 11280378 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/280378
Method of protecting semiconductor chips from mechanical and ESD damage during handling Nov 15, 2005 Issued
Array ( [id] => 573031 [patent_doc_number] => 07459329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Method of fabricating silicon-based MEMS devices' [patent_app_type] => utility [patent_app_number] => 11/254774 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 14800 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459329.pdf [firstpage_image] =>[orig_patent_app_number] => 11254774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254774
Method of fabricating silicon-based MEMS devices Oct 20, 2005 Issued
Array ( [id] => 5776846 [patent_doc_number] => 20060105486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Method of fabricating a liquid crystal display device' [patent_app_type] => utility [patent_app_number] => 11/254764 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 6254 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20060105486.pdf [firstpage_image] =>[orig_patent_app_number] => 11254764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254764
Method of fabricating a liquid crystal display device Oct 20, 2005 Issued
Array ( [id] => 4982986 [patent_doc_number] => 20070087544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Method for forming improved bump structure' [patent_app_type] => utility [patent_app_number] => 11/252764 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2559 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087544.pdf [firstpage_image] =>[orig_patent_app_number] => 11252764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252764
Method for forming improved bump structure Oct 18, 2005 Abandoned
Array ( [id] => 4982967 [patent_doc_number] => 20070087525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate' [patent_app_type] => utility [patent_app_number] => 11/254044 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4201 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087525.pdf [firstpage_image] =>[orig_patent_app_number] => 11254044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254044
Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate Oct 18, 2005 Issued
Array ( [id] => 5743258 [patent_doc_number] => 20060088983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Method of dividing wafer' [patent_app_type] => utility [patent_app_number] => 11/251933 [patent_app_country] => US [patent_app_date] => 2005-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3431 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20060088983.pdf [firstpage_image] =>[orig_patent_app_number] => 11251933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251933
Method of dividing wafer Oct 17, 2005 Abandoned
Array ( [id] => 4982953 [patent_doc_number] => 20070087511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Method for forming an avalanche photodiode' [patent_app_type] => utility [patent_app_number] => 11/251964 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6482 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087511.pdf [firstpage_image] =>[orig_patent_app_number] => 11251964 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251964
Method for forming an avalanche photodiode Oct 16, 2005 Issued
Array ( [id] => 809984 [patent_doc_number] => 07416905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Method of fabricating a magnetic shift register' [patent_app_type] => utility [patent_app_number] => 11/252384 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 80 [patent_no_of_words] => 16899 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/416/07416905.pdf [firstpage_image] =>[orig_patent_app_number] => 11252384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252384
Method of fabricating a magnetic shift register Oct 16, 2005 Issued
Array ( [id] => 5708115 [patent_doc_number] => 20060049459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/250464 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6966 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20060049459.pdf [firstpage_image] =>[orig_patent_app_number] => 11250464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/250464
Manufacturing method of semiconductor device Oct 16, 2005 Issued
Array ( [id] => 5842621 [patent_doc_number] => 20060121257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Method for producing a rewiring printed circuit board' [patent_app_type] => utility [patent_app_number] => 11/251594 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2721 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20060121257.pdf [firstpage_image] =>[orig_patent_app_number] => 11251594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251594
Method for producing a rewiring printed circuit board Oct 13, 2005 Issued
Array ( [id] => 7545381 [patent_doc_number] => 08053352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Method and mesh reference structures for implementing Z-axis cross-talk reduction through copper sputtering onto mesh reference planes' [patent_app_type] => utility [patent_app_number] => 11/250043 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1791 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/053/08053352.pdf [firstpage_image] =>[orig_patent_app_number] => 11250043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/250043
Method and mesh reference structures for implementing Z-axis cross-talk reduction through copper sputtering onto mesh reference planes Oct 12, 2005 Issued
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