Search

Samantha N. Wood

Examiner (ID: 6012, Phone: (571)272-6457 , Office: P/2915 )

Most Active Art Unit
2915
Art Unit(s)
2914, 2915
Total Applications
1312
Issued Applications
1235
Pending Applications
29
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 823583 [patent_doc_number] => 07405138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Manufacturing method of stack-type semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/235354 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 55 [patent_no_of_words] => 6712 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405138.pdf [firstpage_image] =>[orig_patent_app_number] => 11235354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/235354
Manufacturing method of stack-type semiconductor device Sep 26, 2005 Issued
Array ( [id] => 5172004 [patent_doc_number] => 20070072437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method for forming narrow structures in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/235214 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072437.pdf [firstpage_image] =>[orig_patent_app_number] => 11235214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/235214
Method for forming narrow structures in a semiconductor device Sep 26, 2005 Issued
Array ( [id] => 5171905 [patent_doc_number] => 20070072338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method for separating package of WLP' [patent_app_type] => utility [patent_app_number] => 11/235484 [patent_app_country] => US [patent_app_date] => 2005-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2490 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072338.pdf [firstpage_image] =>[orig_patent_app_number] => 11235484 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/235484
Method for separating package of WLP Sep 25, 2005 Abandoned
Array ( [id] => 5171911 [patent_doc_number] => 20070072344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Gel package structural enhancement of compression system board connections' [patent_app_type] => utility [patent_app_number] => 11/234883 [patent_app_country] => US [patent_app_date] => 2005-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4718 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072344.pdf [firstpage_image] =>[orig_patent_app_number] => 11234883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/234883
Method for using gel package structure enhancing thermal dissipation between compressed printed circuit board and heat sink mechanical stiffener Sep 25, 2005 Issued
Array ( [id] => 5637534 [patent_doc_number] => 20060068507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same' [patent_app_type] => utility [patent_app_number] => 11/233363 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20060068507.pdf [firstpage_image] =>[orig_patent_app_number] => 11233363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/233363
Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same Sep 22, 2005 Abandoned
Array ( [id] => 5637632 [patent_doc_number] => 20060068605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Method of manufacturing oxide film and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/233024 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20060068605.pdf [firstpage_image] =>[orig_patent_app_number] => 11233024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/233024
Method of manufacturing oxide film and method of manufacturing semiconductor device Sep 22, 2005 Abandoned
Array ( [id] => 5126001 [patent_doc_number] => 20070238272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Method of aligning carbon nanotubes and method of manufacturing field emission device using the same' [patent_app_type] => utility [patent_app_number] => 11/225174 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2606 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20070238272.pdf [firstpage_image] =>[orig_patent_app_number] => 11225174 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225174
Method of aligning carbon nanotubes and method of manufacturing field emission device using the same Sep 13, 2005 Issued
Array ( [id] => 813693 [patent_doc_number] => 07413965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method of manufacturing a thin-film circuit substrate having penetrating structure, and protecting adhesive tape' [patent_app_type] => utility [patent_app_number] => 11/224924 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7644 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/413/07413965.pdf [firstpage_image] =>[orig_patent_app_number] => 11224924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224924
Method of manufacturing a thin-film circuit substrate having penetrating structure, and protecting adhesive tape Sep 13, 2005 Issued
Array ( [id] => 5793707 [patent_doc_number] => 20060014388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Wafer processing apparatus & methods for depositing cobalt silicide' [patent_app_type] => utility [patent_app_number] => 11/224863 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6196 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20060014388.pdf [firstpage_image] =>[orig_patent_app_number] => 11224863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224863
Wafer processing apparatus & methods for depositing cobalt silicide Sep 11, 2005 Abandoned
Array ( [id] => 341553 [patent_doc_number] => 07501311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Fabrication method of a wafer structure' [patent_app_type] => utility [patent_app_number] => 11/183833 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2321 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501311.pdf [firstpage_image] =>[orig_patent_app_number] => 11183833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183833
Fabrication method of a wafer structure Jul 18, 2005 Issued
Array ( [id] => 559300 [patent_doc_number] => 07161181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Thin film transistor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/183383 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 61 [patent_no_of_words] => 12763 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161181.pdf [firstpage_image] =>[orig_patent_app_number] => 11183383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183383
Thin film transistor device and method of manufacturing the same Jul 17, 2005 Issued
Array ( [id] => 5075368 [patent_doc_number] => 20070015343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Method for dicing a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 11/182794 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1408 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20070015343.pdf [firstpage_image] =>[orig_patent_app_number] => 11182794 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/182794
Method for dicing a semiconductor wafer Jul 17, 2005 Abandoned
Array ( [id] => 609440 [patent_doc_number] => 07151012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-19 [patent_title] => 'Redistribution layer of wafer and the fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 11/183494 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 2757 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151012.pdf [firstpage_image] =>[orig_patent_app_number] => 11183494 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183494
Redistribution layer of wafer and the fabricating method thereof Jul 17, 2005 Issued
Array ( [id] => 5859079 [patent_doc_number] => 20060228870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Method of making group III-V nitride-based semiconductor crystal' [patent_app_type] => utility [patent_app_number] => 11/182074 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3970 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20060228870.pdf [firstpage_image] =>[orig_patent_app_number] => 11182074 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/182074
Method of making group III-V nitride-based semiconductor crystal Jul 14, 2005 Abandoned
Array ( [id] => 573306 [patent_doc_number] => 07459352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Semiconductor device, and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/181923 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 82 [patent_no_of_words] => 31960 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459352.pdf [firstpage_image] =>[orig_patent_app_number] => 11181923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/181923
Semiconductor device, and manufacturing method thereof Jul 14, 2005 Issued
Array ( [id] => 5793692 [patent_doc_number] => 20060014373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method for finishing metal line for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/183093 [patent_app_country] => US [patent_app_date] => 2005-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20060014373.pdf [firstpage_image] =>[orig_patent_app_number] => 11183093 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183093
Method for finishing metal line for semiconductor device Jul 13, 2005 Issued
Array ( [id] => 6978002 [patent_doc_number] => 20050287720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Method of fabricating thin film transistor by reverse process' [patent_app_type] => utility [patent_app_number] => 11/157873 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1676 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287720.pdf [firstpage_image] =>[orig_patent_app_number] => 11157873 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157873
Method of fabricating thin film transistor by reverse process Jun 21, 2005 Abandoned
Array ( [id] => 5688444 [patent_doc_number] => 20060286759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Metal oxide semiconductor (MOS) device having both an accumulation and a enhancement mode transistor device on a similar substrate and a method of manufacture therefor' [patent_app_type] => utility [patent_app_number] => 11/157224 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4405 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286759.pdf [firstpage_image] =>[orig_patent_app_number] => 11157224 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157224
Metal oxide semiconductor (MOS) device having both an accumulation and a enhancement mode transistor device on a similar substrate and a method of manufacture therefor Jun 20, 2005 Abandoned
Array ( [id] => 6963889 [patent_doc_number] => 20050230786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Semiconductor device having a measuring pattern and a method of measuring the semiconductor device using the measuring pattern' [patent_app_type] => utility [patent_app_number] => 11/157534 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4442 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20050230786.pdf [firstpage_image] =>[orig_patent_app_number] => 11157534 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157534
Semiconductor device having a measuring pattern and a method of measuring the semiconductor device using the measuring pattern Jun 20, 2005 Issued
Array ( [id] => 6966696 [patent_doc_number] => 20050233593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Plating of multi-layer structures' [patent_app_type] => utility [patent_app_number] => 11/156544 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3052 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20050233593.pdf [firstpage_image] =>[orig_patent_app_number] => 11156544 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/156544
Plating of multi-layer structures Jun 20, 2005 Issued
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